TAG LO 203 350 Search Results

RM5271

Abstract: RM5200 rm5270 R4700 R5000 31x31 RM5271-200S qed rm5200
Contextual Info: RM5271 Superscalar Microprocessor with External Cache Interface FEATURES • Dual Issue superscalar microprocessor — 200, 225, 250, 266, 300, 350 MHz operating frequencies — 420 Dhrystone 2.1 MIPS maximum — SPECInt95 7.3, SPECfp95 8.3 maximum • High-performance system interface

Contextual Info: QED RISCMark RM5271™ 64-Bit Superscalar Advanced Microprocessor Quantum p j Effect Design, Inc. • Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle - 150, 200, 250, 266 MHz operating frequencies

7000ASC

Abstract: Tag 225 600 replacement 700M RM5261A RM7000A RM5200 R5000 mips
Contextual Info: Standard Products ACT 7000ASC 64-Bit Superscaler Microprocessor October 9, 2009 www.aeroflex.com/Avionics FEATURES • ■ ● 225, 300, 350 MHz operating frequency Consult Factory for latest speeds MIPS IV Superset Instruction Set Architecture ● ● ●

siemens sirius 3r

Abstract: Sprecher Schuh CT 3-12 plotter ip-220 Transformer zkb Sirius 3SB3 sti es 1682 IP220 Legrand symbol electric manual legrand
Contextual Info: Terminal Markers 4 Terminal Markers Almost any marking task involving any type of terminal block can be tackled using the Weidmüller range of terminal markers. Whether a clamping point needs multicharacter marking, ready-to-use markers with standard or custom printing, white or

qed rm5200

Contextual Info: RM5271 Microprocessor with External Cache Interface Document Rev. 1.3 Date: 02/2000 FEATURES • High-performance floating point unit - up to 700 MFLOPS — Single cycle repeat rate for common single precision operations and some double precision operations

R4000

Abstract: RM5200 RM5261A
Contextual Info: :5 3: 26 AM RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary on Tu es da y, 28 Oc to be r, 20 03 02 RM5261A Data Sheet Do wn lo ad ed by m oh am ed fa ro uk o fs ilic on ex pe rt RM5261A™ Microprocessor with 64-Bit System Bus Proprietary and Confidential

Contextual Info: :4 6: 22 AM RM5261A Microprocessor with 64-Bit System Bus Data Sheet Released Tu es da y, 14 Se pt em be r, 20 04 06 RM5261A Data Sheet Do wn lo ad ed by Co nt e nt Te a m of P ar tm in er In co n RM5261A™ Microprocessor with 64-Bit System Bus Proprietary and Confidential

79RC5000

Abstract: RC32364 RC4640 RC4650 RC64474 RC64475 RC3041
Contextual Info: 79RC5000 MULTI-ISSUE 64-BIT MICROPROCESSOR HDWXU WXUHV operationLarge, efficient on-chip caches – 32KB Instruction Cache, 32KB Data Cache – 2-set associative in each cach – Virtually indexed and physically tagged to minimize cache flushes – Write-back and write-through selectable on a per page basis

MIL-S-23190

Abstract: MS90387-3
Contextual Info: System Catalog PANis -S TEEL This Header-18pt. SYSTEM SA# 101N16J-NL Prim e m oving products from PANDUIT are part numbers printed in bold typeface . They are stocked items for r apid response and available from our local distributors. Table of Contents – SA101N16J-NL

6 pin sim holder pinout

Abstract: RM5261-200Q mips r5000
Contextual Info: QED RISCMark RM5261™ 64-Bit Superscalar Microprocessor FEATURES: • Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle — 200, 225, 250, 266 MHz operating frequencies — 345 D hrystone2.1 MIPS

Contextual Info: QED RISCMark RM7000™ 64-Bit Superscalar Advance Microprocessor Quantum Effect Design, Inc. Information • Dual Issue symmetric superscalar microprocessor with instruc­ tion prefetch optimized for system level price/performance - 200, 250, 2 6 6 ,3 0 0 MHz operating frequency

R4000

Abstract: RM5200 RM5261A
Contextual Info: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary RM5261A™ RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Contextual Info: :4 0: 49 PM RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released co n Fr id ay ,2 9O ct ob er ,2 00 4 01 RM5261 Data Sheet Proprietary and Confidential Issue 1, March 2001 Do wn lo ad ed by Co nt e nt T ea m of Pa rtm in er In RM5261™ Microprocessor with 64-Bit

Contextual Info: 07 :2 1: 57 P M RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released In co n Tu es da y, 24 Ja nu ar y, 20 12 RM5261 Data Sheet Proprietary and Confidential Issue 1, March 2001 Do wn lo a de d [c on tro lle d] by Co n te nt Te am of Pa rtm in

Z8016

Abstract: z8000 microprocessor zilog Z8000
Contextual Info: ZILOG 17E I NC D • TTÖ40M3 ~ ' Ÿ ¿ ¿ Ä lS ii 6 a t iä 6 i i i i i i S i i S 8 fe M 00in 30 6 ■ I- S Z - ^ - l ^ Z 8016 Z8000 Z-DTC Direct Memory Access Transfer Controller O ctober 1988 FEATURES ■ M em ory-to-peripheral transfers up to 2.66M bytes per

702 TRANSISTOR npn

Abstract: RF NPN POWER TRANSISTOR C 10-12 GHZ BFR106 UBB773 transistor t 2180 IC 1496 function L7E transistor 22741 transistor s1p 8115, transistor
Contextual Info: m b b s a T a i □ d e s 2 d d 2 3 T « a p x P hilips S e m i c o n d u c t o r s _P ro d u c ^ p e c ific a tio n - N AnER PHILIPS/DISCRETE b?E D NPN 5 GHz wideband transistor ^ BFR106 PINNING

TAG 881

Contextual Info: Preliminary data IXSX50N60AU1 IXSX50N60AU1S IGBT with Diode Combi Pack Short Circuit SOA Capability T 0 - 2 4 7 H o le-less SM D 5 0 N 6 0 A U 1 S Sym bol T e s t C o n d itio n s v CES Tj = 25°C to 150°C 600 V v CGR T ,j = 25°C to 150°C ;' RrF = 1 MO

RM5261-250Q

Abstract: MIPS RM5230
Contextual Info: QED RISCMark RM5261™ 64-Bit Superscalar A d vanced Microprocessor Quantum Effect Design, Inc. • Dual Issue superscalar microprocessor - can issue one Integer and one floating-point instruction per cycle - 150, 200, 250,266 MHz operating frequencies

Contextual Info: Zilog P r o d u c t S p e c i f ic a t io n Z8016 Z8000 Z-DTC Dived Mem ory Access Transfer Controller October 1988 FEATURES • Memory-to-peripheral transfers up to 2.66M bytes per second at 4 MHz. ■ Memory-to-memory transfers up to 1.33M bytes per second at 4 MHz.

R4000

Abstract: RM5200 RM5261A
Contextual Info: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary RM5261A™ RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Preliminary Issue 2, September 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

ACT7000ASC

Contextual Info: ACT-7000ASC 64-Bit Superscaler Microprocessor Features • ■ Full militarized PMC-Sierra RM7000A microprocessor Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance ● ● ■ ● ● ●

TDS-01

Abstract: 0DL4
Contextual Info: HITACHI/ L O G I C / ARRAYS/HEH SIE II • M> ‘ib203 0 0 1 7 > m 201 ■ HIT2 HN58C1001 Series Preliminary 1M 128K x 8-bit) EEPROM B DESCRIPTION The Hitachi HN58C1001 is a 1-Megabit CMOS Electrically Erasable Programmable Read Only Memory (EEPROM) organized

LG concurrent RDRAM

Abstract: LG rdram concurrent concurrent rdram GE RTV 162
Contextual Info: TNETX4020 ThunderSWITCH II 2-PORT 100-/1000-MBIT/S ETHERNET™ SWITCH • Single-Chip 100-/1000-Mbit/s Ethernet™ Switch Device • Supports Pretag Extended Port Awareness on Port 1 • Integrated Physical Coding Sublayer PCS Logic Provides Direct Interface to Gigabit

RM5261

Abstract: R4000 R4650 R5000 RM5200 RM5231
Contextual Info: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released RM5261 RM5261™ Microprocessor with 64-Bit System Bus Data Sheet Proprietary and Confidential Issue 1, March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use