TCO 706 Search Results

CY37256P160-125AI

Abstract: CY37256P208-125NC CY37256P160-83AI
Contextual Info: fax id: 6148 PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features — tS = 4.5 ns — tCO = 5.0 ns Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis

CY37064

Abstract: 032-l CERAMIC LEADLESS CHIP CARRIER CY37032 CY37064V CY7C372 CY7C373 100-PIN
Contextual Info: =mmm!Æ ' ^ r ^ r : c Q PR£um A^ Y CY37064 UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 4.0 ns — tco = 4.0 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ ISR™ JTAG-compliant on-board programming • • • •

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JMNK ♦ PRELIMINARY t t *^ ' < ij / 5; CY37064 UltraLogic 64-Macrocell ISR™ CPLD — ts = 4.0 ns Features — tco = 4.0 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ (ISR™ JTAG-compliant

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- J M N K ♦ t t < ij / 5; PRELIMINARY *^ ' CY37064 UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tco = 4.5 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ (ISR™

EIA standards 783

Abstract: PLL 566 AGX51004-2 PRBS31 SMPTE292M SSTL-18 din 2982 SMPTE-424M TCO 706
Contextual Info: 4. DC and Switching Characteristics AGX51004-2.0 Operating Conditions Arria GX devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in –6 speed grade only. This chapter contains the following sections:

TCO 706

Abstract: GX 6107
Contextual Info: 4. DC and Switching Characteristics AGX51004-1.4 Operating Conditions Arria GX devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in -6 speed grade only. This chapter contains the following sections:

EIA standards 783

Abstract: PLL 566 AGX51004-1 PRBS31 SSTL-18 n e c 2705 TCO 706
Contextual Info: 4. DC & Switching Characteristics AGX51004-1.2 Operating Conditions Arria GX devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in -6 speed grade only. Tables 4–1 through 4–37 provide information on absolute maximum

Contextual Info: 4. DC and Switching Characteristics AGX51004-1.3 Operating Conditions Arria GX devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in -6 speed grade only. This chapter contains the following sections:

Contextual Info: Section I. Arria GX Device Data Sheet This section provides designers with the data sheet specifications for Arria GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference

sun hold rx1 1240

Abstract: TRANSISTOR K 314 j 6815 transistor NT 407 F TRANSISTOR TO 220 AGX51001-1 AGX51002-1 AGX51003-1 AGX51004-1 AGX51005-1 transistor horizontal c 5936
Contextual Info: Arria GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AGX5V1-1.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

RX2 0832

Abstract: UNSIGNED SERIAL DIVIDER using verilog
Contextual Info: Section I. Arria GX Device Data Sheet This section provides designers with the data sheet specifications for Arria GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference

transistor 2a92

Abstract: 2a92 transistor
Contextual Info: Arria GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AGX5V1-1.0 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

prbs parity checker and generator

Abstract: AGX51001-2 0278 xf Verilog DDR memory model
Contextual Info: Section I. Arria GX Device Data Sheet This section provides designers with the data sheet specifications for Arria GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating

AGX51001-1

Contextual Info: Section I. Arria GX Device Data Sheet This section provides designers with the data sheet specifications for Arria GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference

Z0 607 MA GX 652

Abstract: rx2 0851 ccpd 33 CB closed loop position estimation with signal GBA 616 sun hold rx1 1240 AGX51001-2 AGX51002-2 AGX51003-2
Contextual Info: Arria GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 9.1 2.0 December 2009 Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

ZO 607 MA 7A 523

Abstract: B17C verilog code for max1619 AGX51001-1 AGX51002-1 AGX51003-1 AGX51004-1 AGX51005-1 transistor D291 tlc 5421
Contextual Info: Arria GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AGX5V1-1.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

bd 5987

Abstract: 0311 sdc 2008 verilog code pipeline ripple carry adder vhdl code for 16 prbs generator AN418 bc 327 K.D How to convert 4-20 ma two wire transmitter linear handbook AGX51001-2 AGX51002-2
Contextual Info: Arria GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 9.1 2.0 December 2009 Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

Contextual Info: Features • • • • • • • • • • • Industry-standard Architecture 12 ns Maximum Pin-to-pin Delay Zero Power – 25 µA Maximum Standby Power Input Transition Detection CMOS and TTL Compatible Inputs and Outputs Advanced Electrically-erasableTechnology

ATF22LV10C

Abstract: ATF22LV10CQZ ATF22LV10CZ ATF22V10CZ
Contextual Info: Features • • • • • • • • • • • • • • 3.0V to 5.5V Operating Range Lowest Power in It Class Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device “Zero” Standby Power 25 µA Maximum (Input Transition Detection)

g22v10

Abstract: PLD programming ATF22V10C-10PU ATF22V10C-15PU gal programming specification 22V10C ATF22V10C ATF22V10CQ ATF22V10CQZ ATF22V10CZ
Contextual Info: Features • Industry-standard Architecture – Low-cost, Easy-to-use Software Tools • High-speed, Electrically Erasable Programmable Logic Devices – 5 ns Maximum Pin-to-pin Delay • CMOS- and TTL-compatible Inputs and Outputs – Latch Feature Holds Inputs to Previous Logic States

22V10C

Abstract: ATF22LV10C ATF22LV10CQZ ATF22LV10CZ ATF22V10C wincupl g22v10
Contextual Info: Features • • • • • • • • • • • • • • • 3.0V to 5.5V Operating Range Advanced Low-voltage Electrically-erasable Programmable Logic Device User-controlled Power-down Pin Option Pin-controlled Standby Power 10 µA Typical Well-suited for Battery Powered Systems

0735Q

Contextual Info: Features • Industry-standard Architecture – Low-cost, Easy-to-use Software Tools • High-speed, Electrically Erasable Programmable Logic Devices – 5 ns Maximum Pin-to-pin Delay • CMOS- and TTL-compatible Inputs and Outputs – Latch Feature Holds Inputs to Previous Logic States

16R8

Abstract: ATF16LV8C ATF16LV8C-10JC ATF16LV8C-10PC ATF16LV8C-10SC ATF16LV8C-10XC ATF16LV8C-15JC ATF16LV8C-15PC ATF16LV8C-15SC
Contextual Info: Features • 3.0V to 5.5V Operation • Industry-standard Architecture – Emulates Many 20-pin PALs – Low-cost Easy-to-use Software Tools High-speed – 10 ns Maximum Pin-to-pin Delay Ultra-low Power – 5 µA Max Pin-controlled Power-down Mode Option

atmel h 208

Abstract: MC3334
Contextual Info: Features • 2nd Generation EE PROM-based Complex Programmable Logic Devices • • • • • • • • • • – 4.5V to 5.5V Operating Range with I/Os 3.3 or 5V Compliant – 32 - 256 Macrocells with Enhanced Features – Pin-compatible with Industry Standard Devices