TDD41S2 Search Results

CH341A

Abstract: digital trainer schematic diagram laf 0001 CH3401 J0123 ccs ldl HP 3D6 000A75 X77H-X70H TO SI 788 48D
Contextual Info: H i/1 I - = - ^ • QE1F Device Quad E1 Framer TXC-03104 DATA SHEET FEATURES DESCRIPTION • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and

DAX 3S

Contextual Info: L3M Device Level 3 Mapper TXC-03452 DATA SHEET Product Preview i—— = = = = = = = = = = • SDH/SONET bus access: -Drop/add data byte access with clock, C1J1, SPE, and parity -Add bus interface timing derived from drop bus, add bus, or external timing

Contextual Info: t r ä ^ s S w it c h P H A S T -1 D e v ic e SONET STS-1 Overhead Terminator TXC-06101 « DATA SHEET DESCRIPTION FEATURES Provides SONET interface to any type of payload Programmable STS-1 or STS-N modes Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse for

FFD 455

Abstract: CA2270 FFD11 CA-575 marking code FFD CA278 5b S34 SARA-S
Contextual Info: Segmentation SARA Hardware Description SARA Chipset Technical Manual Chapter 3. Hardware Description 3.1 Segmentation SARA Hardware Description 3.1.1 Segmentation SARA Internal Block Description Figure 3-1 shows a block diagram o f the Segmentation S A R A chip.

Contextual Info: DS3F Device DS3 Framer TXC-03401 B DATA SHEET • DS3 payload access, bit-serial or nibble-parallel • C-bit parity or M13 operating mode • C-bit interface 13 C-bits in, 14 out • Detect and generate DS3 AIS, and idle signals • Transmit reference generator for serial operation

Contextual Info: QDS1F Device QUAD DS1 Framer TXC-03102 DATA SHEET Preliminary = • D4 SF, ESF including FDL support , and transparent framing modes DESCRIPTION m ssg.ss=saam .i i = • Detects, counts and forces line code errors (BPVs and excess zeros), CRC errors (ESF

Contextual Info: SALI-25C Device Six ATM Line Interface at 25 Mbit/s TXC-07625 DATA SHEET PRODUCT PREVIEW -•■= • Transmission Convergence - meets ATM Forum specifications - maps ATM cells to six 25.6 Mbit/s payloads - NRZ/NRZI and 5B/4B conversions - scambling, cell delineation and rate adaptation

Contextual Info: E123MUX Device E1/E2/E3 MUX/DEMUX TXC-03361 DATA SHEET PRODUCT PREVIEW = • Multiplexer/demultiplexer for ITU-T Recommendations: G.742 E2 frame format G.751 (E3 frame format) DESCRIPTION = The E123MUX is a CMOS VLSI device that provides the E13 functions needed to multiplex and demultiplex

TT 46 N 16 LOF

Abstract: TXC-03361 88H-8AH MCMI hdb3 Alarm Clock by using ttl c5lsm Digital Alarm Clock by using ttl 4S50 10D41 HDB3 E2
Contextual Info: E123MUX Device y E1/E2/E3 MUX/DEMUX TXC-03361 Z7 Û ÏS IX ] FEATURES DESCRIPTION • Multiplexer/demultiplexer for ITU-T Recommendations: G.742 E2 frame format G.751 (E3 frame format) The E123MUX is a CMOS VLSI device that provides the E13 functions needed to multiplex and demultiplex

suzuki DT4

Abstract: fd 20049 pc 525 R300F TXC-03303-MB DS200F3 llb10 dt28 mod 4 counter SU-210
Contextual Info: M 13E D e vice DS3/DS1 MUX/DEMUX, Extended Features TXC-03303 DATA SHEET Preliminary • Multiplexes/demultiplexes 28 DS1 signals into a DS3 signal. • M13 or C-bit parity mode operation • FEBE, C, or P-bit parity error insertion capability • DS3 idle signal generators

Contextual Info: QE1F Device t r a n S w it c h Quad E1 Framer TXC-03104 DATA SHEET DESCRIPTION FEATURES • Offline framer supports Standard and Frame Hold-Off frame alignment with CRC-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode

Contextual Info: SOT-3 Device STM-1/STS-3/STS-3c Overhead Terminator TXC-03003B DATA SHEET Product Preview DESCRIPTION •.■■■= • Transport Section and Line Overhead byte processing • Independent Path Overhead byte processing • Transmit and receive pointer generation with

Contextual Info: HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary = DESCRIPTION — The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send and receive packets at line rates up to 51.84 Mbit/s using either a nibble, byte-parallel, or serial interface.