TDQ 4 Search Results

XAPP253

Abstract: CLK180 FF1152 MT46V4M32 XC2V3000 trace code micron label
Contextual Info: Application Note: Virtex-II Series R XAPP253 v2.0 July 16, 2002 Synthesizable 400 Mb/s DDR SDRAM Controller Author: Lakshmi Gopalakrishnan Summary This application note describes how to use a Virtex -II device to interface to a Double Data Rate (DDR) SDRAM device. The reference design targets a DDR SDRAM device at a clock

vl82c483

Contextual Info: PRELIMINARY ?/ CYPRESS 128K/256K Cache Module for VLSI VL82C483 Chip Set Features Functional Description • 128 K-byte CYM7450 or 256 K-byte (CYM7451) secondary cache module organized as 32K by 32 o r 64K by 32 • Ideal for Intel 486-based systems

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Order this document by MPC27T416/D MPC27T416 16K x 16 Bit Cache-Tag RAM for PowerPC Processors The M PC 27T 416 is a 26 2,14 4 bit c a c h e -ta g static RAM desig ned to support Pow erPC processors at bus speeds up to 66 M Hz. It is organized as 16K w ords of

vl82c483

Abstract: C1882 CYM7450 203C 74so3 VL82C 128 pin connector c3195 D01711 950 T63
Contextual Info: CYM7450 CYM7451 PRELIMINARY rj f C Y P R E S S 128K/256K Cache M odule for VLSI VL82C483 Chip Set Features Functional Description • 128 K-byte CYM7450 or 256 K-byte (CYM7451) secondary cache module organized as 32K by 32 or 64K by 32 • Ideal for Intel 486-based systems

vhdl sdram

Abstract: CLK180 FD64 PC-100 SRL16 XAPP200 virtex 5 ddr data path V300BG432 signal path designer
Contextual Info: Application Note: Virtex Series and Spartan-II Family R XAPP200 v2.2 February 18, 2000 Synthesizable 1.6 GBytes/s DDR SDRAM Controller Author: Jennifer Tran Summary The DLLs and the SelectI/O features in the Virtex™ architecture and Spartan™-II family

HE2V

Contextual Info: MOTOROLA Order this document SEMICONDUCTOR TECHNICAL DATA by MPC27T416/D MPC27T416 Advance Information 16K x 16 Bit Cache Tag RAM for PowerPC Processors The MPC27T416 is a 262,144 bit cache-tag static RAM designed to support PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as

Contextual Info: MOTOROLA Order this document by MPC27T416/D SEMICONDUCTOR TECHNICAL DATA Advance Information MPC27T416 16K x 16 Bit Cache Tag RAM for PowerPC Processors The MPC27T416 is a 262,144 bit cache–tag static RAM designed to support PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K

Contextual Info: MOTOROLA Order this docum ent by MPC27T416/D SEMICONDUCTOR TECHNICAL DATA MPC27T416 Advance Information 16K x 16 Bit Cache Tag RAM for PowerPC Processors The MPC27T416 is a 262,144 bit cache-tag static RAM designed to support PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K

Contextual Info: Order this document SEMICONDUCTOR TECHNICAL DATA by MPC27T415/D MPC27T415 Advance Information 16K x 15 Bit Cache Tag RAM for PowerPC Processors The MPC27T415 is a 245,760 bit cache-tag static RAM designed to support PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K

Contextual Info: MOTOROLA Order this document by MPC27T415/D SEMICONDUCTOR TECHNICAL DATA Advance Information MPC27T415 16K x 15 Bit Cache Tag RAM for PowerPC Processors The MPC27T415 is a 245,760 bit cache–tag static RAM designed to support PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K

Contextual Info: AFE1256 www.ti.com SBAS630 – OCTOBER 2013 256-Channel, Analog Front-End for Digital X-Ray Flat-Panel Detectors FEATURES DESCRIPTION • • • • • The AFE1256 is a 256-channel, analog front-end designed to suit the requirements of flat-panel detectors FPDs based on digital X-ray systems. The

Contextual Info: SKET 330 THYRISTOR BRIDGE,SCR,BRIDGE SEMIPACK 4 Thyristor Modules SKET 330 Features # $%&' ' & *+%( ',(-./, &0.12)2.1 # )2'(23% 4%(&124 2*-0&'%3 1%'&0 5&*%60&'% 7(%42-.* 1%'&0 6(%*.(% 4-)'&4'* +-( ,2/, (%02&5202'8 9,8(2*'-( :2', &1602+82)/ /&'% ;< (%4-/)2=%3> +20% )-? @ AB CBD

Your Wireless Connection

Abstract: walkie-talkie 900MHz L9320 SATURN walkie-talkie L9002VX L9002VX2 L92VX3-SL
Contextual Info: SATURN-III family L9002VX3 L92VX3-SL SATURN 3rd Generation CD/SS Processor SATURN Low Power 3G CD/SS™ Processor December 2002 1 CD/SS Wireless Phone Extending 1-bit CDMA performance to the Wireless Local Loop l a i t n e d i f n L9002VX3 Performance /

32D531

Abstract: mfm encoder WD2010 namics
Contextual Info: SSI 32D531 jilimMfans Data Separator and Write Precompensation Device May, 1989 FEATURES DESCRIPTION The SSI 32D531 Data Separator performs data syn­ chronization and write precompensation of encoded data. The interface of the SSI 32D531 is optimum for use with W estern Digital's WD1010/WD2010 control­

AD20MSP910

Abstract: AD6435 AD6436 ADSP2181 ADSST-G723 ADSST-G728 ADSST-G729 ADSST-MOD-2010 v.34 fax decode
Contextual Info: DSP: Chip Sets and Reference Designs CHIP SETS MODEL NUMBER ADSST-NAV2000 ADSST-NAV2100 ADSST-G723 ADSST-G728 ADSST-G729 ADSST-MPEG1000 ADSST-MPEG2000 AD20MSP910 AD20MSP400HF AD20MSP410 AD20MSP415 Description CHIP SET FOR FOR GPS RECEIVER, SHARC BASED GLOSSY

02S00

Contextual Info: QSFCT191T, QSFCT2191T Ò High Speed CMOS Presettable Synchronous 4-Bit Binary Counters qs54/74fcti9it q s 54/74f c t 219 i t FEATURES/BENEFITS • Pin and function compatible to the 74F191 74FCT191 and 74FCT191T • CMOS power levels: <7.5 mW static • Available in DIP, SOIC, QSOP, ZIP, HQSOP

PS2085A

Contextual Info: fH PER ICOM ADVANCE INFORMATION PI74FCT193T 25ft Series PI74FCT2193T i in in in in in in in in in in in in in in in ii in in in in in in in in in in in in in in in in in in in in in in in in in in in in i High Speed CMOS Presettable Synchronous 4-Bit Binary Counters

NT5CB256

Abstract: NT5CC256M16CP-DI NT5CB256M16 NT5CB256m NT5CB512M8CN-DI NT5CB256M16CP-DI NT5CC512M8CN-DI NT5CC512M8CN-DII NT5CB256M16CP-EK NT5CC512M8
Contextual Info: 4Gb DDR3 SDRAM C-Die NT5CB512M8CN / NT5CB256M16CP NT5CC512M8CN / NT5CC256M16CP CAS Latency Frequency -DI/DII* -EK* -FL* DDR3/L-1600-CL11 DDR3-1866-CL13 DDR3-2133-CL14 Min. Min. Speed Bins Units tCK Parameter Max. Max. Min. Max. Avg Clock Frequency 300 800

Contextual Info: QSFCT193T, 2193T Q QS54/74FCT193T High Speed CMOS Presettable Synchronous 4-Bit Binary Counters QS54/74FCT2193T FEATURES/BENEFITS TTL-compatible input and output levels Ground bounce controlled outputs Reduced output swing of 0-3.5V Military product compliant to MIL-STD-883

Contextual Info: H PERI COM PI74FCT191T (25ft Series PI74FCT2191T iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii High Speed CMOS Presettable Synchronous 4-Bit Binary Counters Product Features: Product Description: • PI74FCT191/2191T is pin compatible with bipolar FAST

Contextual Info: fH PER ICOM ADVANCE INFORMATION PI74FCT191T 25ft Series PI74FCT2191T i in in in in in in in in in in in in in in in ii in in in in in in in in in in in in in in in in in in in in in in in in in in in in i High Speed CMOS Presettable Synchronous 4-Bit Binary Counters

3 pin smd 24c

Abstract: mx1a op 30MHZ xfmrs rev.a JEM2
Contextual Info: 1. Mechanical Dimensions: 3. E l e c t r i c a l S p e c i f i c a t i o n s : 25°C 15.8D Max Insertion Loss: □ □ Return Loss: XFMRS YYWW I.OdB Mox @1—100MHz -1 8 d B Min, @ 1-30M Hz - 1 BdB Min, ©40MHz —1 BdB Min, @50MHz —1 ZdB Min, @60—60MHz

Contextual Info: f j j PER ICOM PI74FCT191T 25Q Series PI74FCT2191T High Speed CMOS Presettable Synchronous 4-Bit Binary Counters Product Features: Product Description: • PI74FCT191/2191T is pin compatible with bipolar FAS T

Contextual Info: P ow er F-M O S F E T 2SK809, 2SK809A 2SK809, 2SK809A Silicon N-channel Power F-M O S F E T Package Dim ensions • Features • L o w O N r e s i s t a n c e Rds o n : R ds (o n ) = 1 . 5 f t ( t y p .) Unit: mm • H ig h s w itc h in g r a t e : tf = 8 5 n s ( ty p .)