TIL 127 DATASHEET Search Results

Contextual Info: ISL95310 Digitally Controlled Potentiometer XDCP Datasheet May 6, 2005 Terminal Voltage 0V to 13.2V, 128 Taps Up/Down Interface Features • Non-volatile solid-state potentiometer The Intersil ISL95310 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper

ISL95310

Abstract: ISL95310UIU10Z ISL95310WIU10Z MO-187BA
Contextual Info: ISL95310 Digitally Controlled Potentiometer XDCP Datasheet May 6, 2005 Terminal Voltage 0V to 13.2V, 128 Taps Up/Down Interface Features • Non-volatile solid-state potentiometer The Intersil ISL95310 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper

Contextual Info: ISL95310 Digitally Controlled Potentiometer XDCP Datasheet PRELIMINARY May 6, 2005 Terminal Voltage 0V to 13.2V, 128 Taps Up/Down Interface Features • Non-Volatile Solid-State Potentiometer The Intersil ISL95310 is a digitally controlled potentiometer

ltsx

Contextual Info: Universal Timeslot Interchange — rw & i * — mmi Data Sheet Prelim inary Inform ation November 1997 V LSTechnology I lijf DataSheet SC2000 Universal Timeslot Interchange Table of Contents F e a t u r e s .

Contextual Info: D S 0 4 -2 1 2 0 4 -6 a E . MB87006A DATASHEET = Frequency Synthesizer CMOS Serial Input Phase Locked Loop PLL CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL) FREQUENCY SYNTHESIZER The Fujitsu MB87006A, fabricated in CMOS technology, is a serial input Phase Locked Loop

WMS7110010P

Abstract: 7111 10KOHM 50KOHM WMS7110 WMS7111
Contextual Info: PRELIMINARY DATASHEET WMS7110 / 7111 NON-VOLATILE DIGITAL POTENTIOMETERS WITH UP/DOWN 3-WIRE INTERFACE, 10KOHM, 50KOHM, 100KOHM RESISTANCE 128 TAPS WITHOUT / WITH OUTPUT BUFFER -1- Publication Release Date: July 2003 Revision 1.0 WMS7110 / 7111 1. GENERAL DESCRIPTION

Contextual Info: PSoC Creator Component Datasheet Pseudo Random Sequence PRS 2.0 Features • 2 to 64 bits PRS sequence length • Time Division Multiplexing mode  Serial output bit stream  Continuous or single-step run modes  Standard or custom polynomial

ic 81256 ram

Abstract: mb81256 3GJK 66010-2
Contextual Info: February 1990 Edition 2.0 FUJITSU DATASHEET M B 8 1 2 5 6 -8 0 MOS 262,144 BIT DYNAMIC RANDOM ACCESS MEMORY 262,144 Bit Dynamic Random Access Memory The Fujitsu MB81256 is a fully decoded, dynamic NMOS random access memory organized as 262,144 one-bit words. The design is optimized for high speed,

a36 smd transistor

Abstract: transistor smd 4z
Contextual Info: ÖUALITY'TECHNOLOGIES CORP QUALITY TECHNOLOGIES 27E D 74fe.bfl51 0003431 3 VDE APPROVED PHOTOTRANSISTOR OPTOCOUPLERS < != > CNY17-1/1Z CN Y17-3/3Z C N Y17-2/2Z CN Y17-4/4Z DESCRIPTION PACKAGE DIMENSIONS The CNY17 series consists of a Gallium Arsenide IRED

8X8 INC

Abstract: 8x8 vcp LVP 47-10-43 LD8213 8x8 vcp tse 1885 40BS CCIR601 YUV422 8x83404
Contextual Info: 8x8, Inc. 8x83404 LVP DATASHEET 8x8 LVP Lowbitrate Videophone Processor OVERVIEW The 8x8 LVP i a single-chip programmable low bitrate video phone processor. A member of 8x8's MPA Multimedia Processor Architecture family, it forms the heart of either a PC-based or stand-alone

Contextual Info: PSoC Creator Component Datasheet Timer 2.20 Features • Fixed-function FF and universal digital block (UDB) implementations •    8-, 16-, 24-, or 32-bit timer Optional capture input Enable, trigger, and reset inputs, for synchronizing with other components

Contextual Info: W ie te l Preüminary - m v1 . 2 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput

psoc full projects

Contextual Info: PSoC Creator Component Datasheet Pulse Width Modulator PWM 2.10 Features • 8- or 16-bit resolution • Multiple pulse width output modes  Configurable trigger  Configurable capture  Configurable hardware/software enable  Configurable dead band

388F

Contextual Info: ADSP-2171 November 1993 For current information contact Analog Devices at 617 461-3881 ADSP-2171 DSP Microc FEATURES • 30 ns Instruction Cycle Time from 16.67 MHz Crystal <1 5.0 Volts • 33 MIPS Sustained Performance • ADSP-2100 Family Code & Function Compatible with

Contextual Info: ADVANCE 32 MEG X 72 REGISTERED SDRAM DIMM MICRON8 I TEOWOLOOV, INC. MT36LSDT3272 SYNCHRONOUS DRAM MODULE F o r the late st data sheet revisions, plea se re fe r to the Micron Web site: w w w .m icron.com /m ti/m sp/htm l/datasheet.htm l PIN ASSIGNMENT Front View

Contextual Info: ADVANCE MICRON8 I 64 MEG X 72 REGISTERED SDRAM DIMM TEOWOLOOV, INC. MT36LSDT6472 SYNCHRONOUS DRAM MODULE F o r the late st data sheet revisions, plea se re fe r to the Micron Web site: w w w .m icron.com /m ti/m sp/htm l/datasheet.htm l FEATURES PIN ASSIGNMENT Front View

Contextual Info: ADVANCE MICRON1 32 M EGx72 I SDRAM DIMM SYNCHRONOUS DRAM MODULE M T 18L S D T 3272A F o r the late st data sheet revisions, plea se re fe r to the Micron Web site: w w w .m icron.com /m ti/m sp/htm l/datasheet.htm l FEATURES PIN ASSIGNMENT Front View 168-Pin DIMM

Contextual Info: ADVANCE MICRON8 I 32 MEG X 72 REGISTERED SDRAM DIMM TEOWOLOOV, INC. MT18LSDT3272 SYNCHRONOUS DRAM MODULE F o r the late st data sheet revisions, plea se re fe r to the Micron Web site: w w w .m icron.com /m ti/m sp/htm l/datasheet.htm l FEATURES PIN ASSIGNMENT Front View

845 bios chip

Abstract: Phoenix BIOS Programming Instructions JREX-PM JAP0034 CRISIS EISA by Edward Solari jumptec JRex JIDA 82801DB bios programmer
Contextual Info: JRex-PM Product Manual Document Revision 1.0 JRex-PM Product Manual www.j-rex.com CONTENTS 1. USER 1.1 ABOUT THIS MANUAL .4

byz 71

Abstract: 7.1 subwoofer pcb
Contextual Info: ^ M I C R O N A S Edition March 16,1998 6251-469-1PD INTERMETALL 4 b ñ 2 7 1 1 D 0 0 7 1 E 4 ITT BSP 3501C PRELIMINARY DATASHEET Contents Page Section Title 3 4 4 1. 1.1. 1.2. Introduction Features of the DSP-Section Features of the Analog Section 5 6 6 2.

substitute diode PH 33D

Abstract: ECL 10131 TETRA monitoring
Contextual Info: PMC-Sierra, Inc. PM5351 S/UNI-TETRA S/UNI-TETRA DATASHEET PMC-1971240 ISSUE 6 SATURN USER NETWORK INTERFACE 155-TETRA PM5351 S/UNI- 155-TETRA S/UNI-TETRA SATURN USER NETWORK INTERFACE (155-TETRA) DATASHEET ISSUE 6: DEC 1999 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

tms 0119

Contextual Info: Lattice ispLSr 3192 ;Semiconductor I Corporation High Density Programmable Logic Features IH B • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

7MB6098

Abstract: LT17 IDT7MB6098
Contextual Info: *4055771 D Q 1 4 S n Hfl • IDT bflE 128KB SECONDARY CACHE MODULE FOR THE INTEL i486 IDT7MB6098A INTEGRATED DEVICE Integrated Device Technology, Inc. FEATURES DESCRIPTION • Pin compatible with the Intel 485TurboCache™ 82485MB • 128KB direct mapped, write-through, non-sectored, zerowait-state secondary cache module

TETRA monitoring

Abstract: KT 208 sierra MKT 347 0.01Uf diagram LG LCD TV circuits alarm management in TETRA M 1661 S TZB 36b G781 RELAY 6V 100OHM K2158
Contextual Info: PMC-Sierra, Inc. PM5351 S/UNI-TETRA S/UNI-TETRA DATASHEET PMC-1971240 ISSUE 7 SATURN USER NETWORK INTERFACE 155-TETRA PM5351 S/UNI- 155-TETRA S/UNI-TETRA SATURN USER NETWORK INTERFACE (155-TETRA) DATA SHEET ISSUE 7: FEBRUARY 2000 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000