TN0606 Search Results

TN0606N7

Contextual Info: TN0606N6 _ TN0606N7 _Low ThreshoB N-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information Order Number / Package b v dss/ ^DS ON b v dgs (max) 14-Pin P-Dip 14-Pin C-Dip* 60V 1.5Q TN0606N6 TN0606N7

TN0606N7

Abstract: 2T-3
Contextual Info: G à S u p e r te x in c TN0606 TN0610 . Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information R q S ON (max) Order Num ber / Package f b v dgs V GS(ttl) i B V DSS/ (max) TO-39 TO-92 TO-220 Quad P-DIP Quad C-DIP* DICEt 60V 1.5Q

TN0606

Contextual Info: TN0606 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 45 45 11 ± 1.5 Au 1 (mils) TN0606 1 (mils) Back Side Bonding Pad Material Bond Wire Bond Wire Size Drain Al/Cu/Si

Contextual Info: TN0606N3 Transistors N-Channel Enhancement MOSFET Military/High-RelN V BR DSS (V)60 V(BR)GSS (V)20 I(D) Max. (A)800m I(DM) Max. (A) Pulsed I(D) @Temp (øC) IDM Max (@25øC Amb)3.2 @Pulse Width (s) (Condition)300u Absolute Max. Power Diss. (W)1.0 Minimum Operating Temp (øC)-55

TN0520N3

Abstract: TN0602N2 TN0204N2 TN0524N2 tn0620n2 TN0202N3 TN0202ND TN0204N3 TN0204ND TN0520N2
Contextual Info: - 332 - f Ta=25cC y Vds m % tt € or f Vdg it TN0202N2 TN0202N3 TN0202ND TNQ2Q4N2 TN0204N3 TN0204ND TN0520N2 TN0520N3 TN0520ND TN0524N2 TN0524N3 TN0524ND TN0602N2 TNÛ6Q2N3 TN0602ND TN06Û4N2 TN0604N3 TN0604ND TN0604WG TN0606N2 TN0606N3 TN0606N5 TN06O6NO

TN0606

Abstract: marking TN
Contextual Info: TN0606 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

Contextual Info: TN0606 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

Contextual Info: 1998 • SHORT FORM CATALOG - Revision SENSITRON SEMICONDUCTOR SHD23401 - 60 Volt - Similar to Industry Standard TN0606-001 SHD274002 -100 Volt - Similar to Industry Standard TN2510-002 QUAD, N-CHANNEL ENHANCEMENT-MODE VERTICAL DMOSFETs Features: • • •

TN0606

Abstract: TN0606N3 TN0606N5 TN0610 TN0610N3
Contextual Info: TN0606 TN0610 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / RDS ON BVDGS (max) † ID(ON) (min) VGS(th) (max) Order Number / Package TO-92 TO-220 60V 1.5Ω 3.0A 2.0V TN0606N3 TN0606N5 100V 1.5Ω 3.0A 2.0V TN0610N3

Contextual Info: TN0606 TN0610 Supertex inc. Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information R dS ON Id(ON) ^GSIth) (m ax) (min) (max) TO-39 TO-92 TO-220 Quad P-DIP* Quad C-DIP* 60V 1.5 0 3.0A 1.6V — TN0606N3 TN0606N5 TN0606N6 TN0606N7

Contextual Info: TN0606 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description Low threshold - 2.0V max. High input impedance Low input capacitance - 100pF typical Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage

TN0606

Contextual Info: Supertex inc. TN0606 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 45 45 11 ± 1.5 Au 1 (mils) TN0606 1 (mils) Back Side Bonding Pad Material Drain Al/Cu/Si Bonding Pad Description

Contextual Info: Supertex inc. TN0606 N-Channel Enhancement-Mode Vertical DMOS FET General Description Features ►► ►► ►► ►► ►► ►► ►► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s

TN0606N6

Abstract: TN0606 TN0606N7 FAST DMOS FET Switches DIP PACKAGE ELECTRICAL data Supertex Quad
Contextual Info: TN0606 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information Order Number / Package BVDSS / BVDGS RDS ON (max) 14-Pin P-Dip 14-Pin C-Dip* 60V 1.5Ω TN0606N6 TN0606N7 * 14 pin side brazed ceramic DIP Advanced DMOS Technology

TN0606

Abstract: TN0606N2 TN0606N3 TN0606N5 TN0606N6 TN0606N7 TN0606ND TN0610 TN0610N2 TN0610N3
Contextual Info: TN0606 TN0610 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / RDS ON BVDGS (max) Order Number / Package ID(ON) (min) VGS(th) (max) TO-39 TO-92 TO-220 Quad P-DIP Quad C-DIP* DICE† 60V 1.5Ω 3.0A 1.6V TN0606N2 TN0606N3

TN0606N7

Abstract: TN0606N6 16AS25 14-PIN
Contextual Info: TN0606N6 TN0606N7 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information Order Number / Package BVDSS / BVDGS RDS ON (max) 14-Pin P-Dip 14-Pin C-Dip* 60V 1.5Ω TN0606N6 TN0606N7 * 14 pin side brazed ceramic DIP Advanced DMOS Technology

Contextual Info: TN0606 TN0610 _ N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVdss / R d S ON Order Number / Package I d (ON) ^GS(th) BVdgs (max) (min) (max) TO-39 TO-92 TO-220 Quad P-DIP Quad C-DIP* 60V 1.5Q 3.0A 1.6V TN0606N2 TN0606N3 TN0606N5 TN0606N6

Contextual Info: TN0606N6 TN0606N7 Lj Supertex ÎH|-_ L ow T h r e s h o ld N-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information Standard Commercial Devices Order Number / Package bC 60V max) 14-Pin P-Dip 14-Pin C-Dip* 1.50 TN0606N6 TN0606N7 * 14 pin side brazed ceramic DIP

Contextual Info: TN0606 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This

Contextual Info: TN0606N6 Transistors N-Channel Enhancement Mode MOSFET Array Military/High-RelN V BR DSS (V)60 V(BR)GSS (V)20 I(D) Max. (A)1.4 I(DM) Max. (A) Pulsed I(D) @Temp (øC) IDM Max (@25øC Amb)6.0 @Pulse Width (s) (Condition)300u Absolute Max. Power Diss. (W)3.0

TN0606

Abstract: TN0606N3 TN0606N5 TN0606N6 TN0606N7 TN0610 TN0610N2 TN0610N3 TN0610N5 TN0606N
Contextual Info: TN0606 TN0610 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / RDS ON BVDGS (max) Order Number / Package ID(ON) (min) VGS(th) (max) TO-39 TO-92 TO-220 Quad P-DIP* Quad C-DIP* 60V 1.5Ω 3.0A 1.6V — TN0606N3 TN0606N5

TN0606N7

Contextual Info: ^ Supertex inc. TN0606N6 TN0606N7 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FET Quad Array Ordering Information Order Number / Package b v dss/ BVdos max 14-Pin P-Dip 14-Pin C-Dip* 60V 1.5£i TN0606N6 TN0606N7 * 14 pin side b ra z e d ceram ic D IP

Contextual Info: TN0606 TN0610 _ Low Threshold S u p e r t e x ilK N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information b v dss/ R d S ON I d (ON) ^GS(th) O rder Num ber / Package b v dgs (max) (min) (max) TO-92 TO-220 60V 1.5Q 3.0A 2.0V

Contextual Info: TN0606 TN0610 Low Threshold N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information BVDSS / BVDGS RDS ON (max) ID(ON) (min) VGS(th) (max) Order Number / Package 60V 1.5Ω 3.0A 2.0V TN0606N3 100V 1.5Ω 3.0A 2.0V TN0610N3 TO-92 Features Low Threshold DMOS Technology