TNRP Search Results

TH4B

Contextual Info: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET • • • • • • • • • • • • • • • • • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis

Contextual Info: Rev. 1.21. Apr. 2012 M474B5173BH0 M474B1G73BH0 204pin Unbuffered ECC SODIMM based on 4Gb B-die 78FBGA with Lead-Free & Halogen-Free RoHS compliant datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.

NT5TU128M8DE

Abstract: NT5TU64M16DG nt5tu64m16dg-Bd NT5TU128M8DE-BD NT5TU256M4DE nt5tu64m NT5TU64M16 NT5TU64M16DG-3C NT5TU64M16DG-3CI NT5TU64M16DG-BE
Contextual Info: NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG NT5TB256M4DE / NT5TB128M8DE / NT5TB64M16DG 1Gb DDR2 SDRAM Feature CAS Latency Frequency -37B/-37BI -3C/-3CI -AD/-ADI -AC/-ACI/-ACL -BE -BD DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 DDR2-1066 4-4-4 5-5-5 6-6-6

busy tone detector

Abstract: ampop FX663 FX663D4 FX663P3 ampop rail
Contextual Info: CML Semiconductor Products Call Progress Decoder FX663 D/663/3 January 1999 1.0 • Features Decodes Call Progress Tones Worldwide covering: • • • • 1.1 Single and Dual Tones Fax and Modem Answer/Originate Tones Special Information Tones Fast 'US Busy' Tone Detector

W971GG6JB

Abstract: 8X12 DDR2-667 DDR2-800 0A80
Contextual Info: W971GG6JB 8M  8 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

k4b2g1646q

Abstract: ddr3 2133 K4B2G1646Q-BCK0 K4B2G1646Q-BCMA
Contextual Info: Rev. 1.03, Mar. 2014 K4B2G1646Q 2Gb Q-die DDR3 SDRAM Only x16 96FBGA with Lead-Free & Halogen-Free RoHS compliant datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed

IS46TR

Abstract: IS43TR82560A DDR3 DRAM 2GB 128Mx16 96BALL FBGA "2Gb DDR3 SDRAM"
Contextual Info: IS43/46TR16128A/AL, IS43/46TR82560A/AL 256Mx8, 128Mx16 2Gb DDR3 SDRAM ADVANCED INFORMATION MAY 2012 FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  Low Voltage L : VDD and VDDQ = 1.35V + 0.1V, -0.067V        

Contextual Info: Rev. 1.51, Apr. 2013 M471B5173BH0 M471B1G73BH0 204pin Unbuffered SODIMM based on 4Gb B-die 1.35V 78FBGA with Lead-Free & Halogen-Free RoHS compliant datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.

Contextual Info: 3D Glasses 8-bit Flash Type MCU HT45FH3T Revision: V1.10 Date: ������������ May 17, 2013 HT45FH3T 3D Glasses 8-bit Flash Type MCU Table of Contents Features. 6

Contextual Info: TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM HT67F30/HT67F40/HT67F50/HT67F60 Revision: V1.90 Date: ����������������� December 19, 2013 HT67F30/HT67F40/HT67F50/HT67F60 TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Contextual Info: Ultrasonic Park Assist 8-bit Flash MCU HT45F39 Revision: V1.00 Date: ���������������� October 30, 2013 HT45F39 Ultrasonic Park Assist 8-bit Flash MCU Table of Contents Features. 5

Contextual Info: Enhanced I/O Flash Type MCU with EEPROM HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Revision: 1.80 Date: January 9, 2013 Contents Table of Contents Technical Document .8

Contextual Info: W632GU6KB 16M  8 BANKS  16 BIT DDR3L SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

Contextual Info: W631GU6KB 8M  8 BANKS  16 BIT DDR3L SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

Contextual Info: ESMT M14D5121632A 2H Operation Temperature Condition (TC) -40°C~95°C DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z VDD = 1.75V ~ 1.9V, VDDQ = 1.75V ~ 1.9V (for speed grade -1.8) z

M14D1G166

Abstract: m14d1g M14D1G1664A m14d1g16 DDRII esmt
Contextual Info: ESMT M14D1G1664A 2D 7DDR II SDRAM 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

NT5CB64M16AP-CF

Abstract: nt5cb64m16 NT5CB64M16AP-CG NT5CB64M16AP nanya NT5CB64M16AP NT5CB64m NT5CB64M16AP-BE nt5cb64m16ap-dh MPR 20 20 CF RESISTOR NT5CB64M16AP-AC
Contextual Info: 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature  Write Leveling  1.5V ± 0.075V JEDEC Standard Power Supply  OCD Calibration  8 Internal memory banks (BA0- BA2)  Dynamic ODT (Rtt_Nom & Rtt_WR)  Differential clock input (CK, )

W631GG6KB-12

Abstract: W631GG6KB-15 W631GG6KB15A DDR3 DIMM SPD JEDEC 24si 9x13 W631GG6KB15K w631gg6k W631GG6KB12I W631GG6KB-15I
Contextual Info: W631GG6KB 8M  8 BANKS  16 BIT DDR3 SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

Contextual Info: W9712G6KB 2M  4 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

W971GG6KB

Abstract: W971GG6KB-3 W971GG6KB-25 W971GG6KB25
Contextual Info: W971GG6KB 8M  8 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

W631GU8KB15K

Contextual Info: W631GU8KB 16M  8 BANKS  8 BIT DDR3L SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

W632GG6KB

Abstract: W632GG6KB15I
Contextual Info: W632GG6KB 16M  8 BANKS  16 BIT DDR3 SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

W3J512M32G

Abstract: M41K256M32
Contextual Info: W3J512M32G-XBX W3J512M32G T -XB2X W3J512M36/40G(T)-XB3X *PRELIMINARY 2GB – 512M x 32/36/40 DDR3 SDRAM 1.5V – 136/204 PBGA Multi-Chip Package FEATURES BENEFITS  DDR3 Data Rate = 800, 1,066, 1333 Mb/s  74% Space savings vs. FBGA  Packages:

Contextual Info: W3J512M64K-XPBX W3J512M64K-XLBX *ADVANCED 4GB – 512M x 64 DDR3 SDRAM 1.35V – 543 PBGA Multi-Chip Package FEATURES  Address/control terminations included  DDR3 Data Rate = 800, 1,066, 1333, 1600* Mb/s  Differential clock terminations included