TOGGLE TYPE FLIP FLOP IC Search Results

Single Toggle Flip Flop

Abstract: AT40K AT40KAL AT94K AT94KAL Single T-Type Flip-Flop
Contextual Info: IP Core Generator: Flip-Flop Features • Flip-Flop – D-Type • Flip-Flop – Toggle • Accessible from the Macro Generator Dialog and HDLPlanner – Included in IDS for • • • • • • • • • FPGA Devices and System Designer™ for AT94K FPSLIC™ Devices

Contextual Info: SY10E131 SYNERG Y 4-BIT D FLIP-FLOP OTlUltlJl SEMICONDUCTOR DESCRIPTION FEATURES • 1100 MHz min. toggle frequency. The SY10E/100E/101E131 is a high speed quad master-slave D-type flip- flop with differential outputs designed for use in new high performance ECL systems. The flip-flops may be individually

cd40138

Abstract: CD4013B RCA-CD4013B CD4013BH d flipflop 15-V
Contextual Info: CD4013B Types Features: CMOS Dual ‘D’-Type Flip-Flop • Set-Reset capability ■ Static flip-flop operation — retains state indefinitely with clock level either "high" or "low ” ■ Medium-speed operation — 16 MHz typ. clock toggle rate at 10V

14013B

Contextual Info: H D 14013B Dual D -ty p e Flip Flop The HD14013B dual type D flip-flop has independent Data, D , Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip-flops for counter and toggle

DDD1173

Abstract: SY100E131 SY10E131
Contextual Info: * SYNERGY S E M IC O N D U C T O R SY10E131 SY100E131 4-BIT D FLIP-FLOP FEATURES DESCRIPTION 1100MHz min. toggle frequency The SY10/100E131 are high-speed quad m aster slave D-type flip-flops with differential outputs designed for use in new, high-perform ance ECL system s. The flip -flop s may

MC1690L

Abstract: 98903 d flipflop 11C06 98906
Contextual Info: 11C06 JSgl National Æ Æ Semiconductor 11C06 750 MHz D-Type Flip-Flop General Description The 11C06 is a high-speed ECL D-Type Master-Slave Flip­ Flop capable of toggle rates over 750 MHz. Designed pri­ marily for high-speed prescaling, it can also be used in any

11C70

Abstract: F100K MC1670
Contextual Info: 11C70 WA National SÌA Semiconductor 11C70 Master-Slave D-Type Flip-Flop General Description T he 11C70 is a high-speed ECL D-Type M aster-Slave Flip­ Flop capable o f toggle rates over 6 50 MHz. Designed pri­ m arily fo r com m unications and instrum entation, it can also

F100K

Abstract: SY100S331 SY100S331DC
Contextual Info: * SYNERGY TRIPLE D FLIP-FLOP SY100S331 S E M IC O N D U C T O R FEATURES DESCRIPTION I Max. toggle frequency of 800MHz I Differential outputs I I e e min. of -80m A The SY100S331 offers three D-type, edge-triggered m aster/slave flip -flop s with true and com plem ent outputs,

CD 40138

Abstract: tc 40138 ic 40138 of the IC CD4013B cd40138 40138 cmos 40138
Contextual Info: C 0 ^ « ilT y p e s 4 - O /S ß Features: CMOS Dual ‘D’-Type Flip-Flop • Set-Reset capability * Static flip-flop operation — retains state indefinitely with dock level either "high" or "low" ■ Medium-speed operation - 16 MHz typ. dock toggle rate at 10V

Contextual Info: * HEX D FLIP-FLOP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 700MHz The SY100S351 offers six D-type, edge-triggered, m aster/slave flip-flops with differential outputs, and is designed for use in high-perform ance ECL system s. The

7z93134

Abstract: 74HC 74HCT 7z93131
Contextual Info: 74HC/HCT109 flip-flops D U A L JK FLIP-FLOP W ITH SET A N D RESET; POSITIVE-EDGE TR IG G ER FEATURES • • TYPICAL J, K inputs fo r easy D-type flip -flo p Toggle flip -flo p or "d o nothing" mode O utput capability: standard l£ £ category: flip-flops

MC1690L

Abstract: F11C06
Contextual Info: 11C06 750 MHz D-TYPE FLIP-FLOP 1 1 C 0 0 S E R IE S GENERAL DESCRIPTION — The F11C06 is a high speed ECL D-type Master-Slave Flip-Flop capable of toggle rates over 750 MHz. Designed prim arily for high speed pre­ scaling, it can also be used in any application which does not require preset inputs. The

Contextual Info: « SY100S331 TRIPLE D FLIP-FLOP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 800MHz The SY100S331 offers three D-type, edge-triggered m aster/slave flip-flops with true and com plem ent outputs, designed for use in high-perform ance ECL system s. Each

6A07

Abstract: IW4013B
Contextual Info: IW4013B Description The IW4013B consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Qoutput to the data input,for counter and toggle applications. The logic level present at the

11C70DC

Contextual Info: 11C70 MASTER/SLAVE D FLIP-FLOP 1 1 C 0 0 SERIES G E N E R A L D E S C R IP T IO N - The 11C70 is a high-speed ECL D Type M a ste r/S la ve Flip-Flop capable of toggle rates over 6 5 0 MHz. Designed p rim a rily fo r com m unica tions and ins tru m e n ta tio n , it can also be used in o th e r d ig ita l a p plication s and is fu lly co m ­

6 pin sim

Contextual Info: F A I R C H 11C 70 l ^ M a s te r - S la v e D - T y p e A Schlumberger Company F lip - F lo p 11C ECL Product Description The 11C70 is a high-speed ECL D-Type Master-Slave Flip-Flop capable of toggle rates over 650 MHz. Designed prim arily for com m unications and instrum entation, it can

JK flipflop 9001

Abstract: 9022dc DTL9932 9020DC TTL 9020 9000DC 9000DM 9000FC 9000FM 9001FC
Contextual Info: 9XXX Series CONNECTION DIAGRAMS P IN O U T A 9000 • 9001 9020 • 2222Jw ' ° r\ i f . v JK FLIP-FLOPS COO, ’01 DUAL JK FLIP-FLOPS ’20, ’22) 14] Vcc O R D E R IN G C O D E: See Section 9 PIN PKQS Ceram ic U IP ( D) Flatpak IP) OUT MILITARY GRADE

crc-16 implementation

Abstract: toggle type flip flop ic
Contextual Info: TEKTRONIX INC/ TRI ÛUINT EbE D Ì[Q G igaB St B ÔTQbSlô QQ00405 4 EiTRÖ 10G024 10G024K L o g ic Quad D Flip Flop with XOR Inputs 1.9 GHz Clock Rate 10G PicoLogic Family_ FEATURES • Temperature and voltage compensated design • < 50 ps clock to output delay skew

toggle type flip flop ic

Abstract: Toggle flip flop IC
Contextual Info: «o» S Y N ER G Y T RI P L E D H J P - F L û viüUb.i3i S E M IC O N D U C T O R F EA TU R E S D E S C R IP TIO N Max. toggle frequency of 800MHz Differential outputs I ee min. of -8 0 m A Industry standard 100K ECL levels Extended supply voltage option:

hc163a

Contextual Info: MC74HC161A, MC74HC163A Presettable Counters High−Performance Silicon−Gate CMOS The MC74HC161A and HC163A are identical in pinout to the LS161 and LS163. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with

siemens master drive circuit diagram

Abstract: SR flip flop IC toshiba tc110g TC110G jk flip flop to d flip flop conversion SC11C1 JK flip flop IC siemens Nand gate scxc1 SR flip flop IC pin diagram
Contextual Info: SIEM EN S ASIC Product Description SCxC1 Family CMOS Gate Arrays FEATURES • Alternate source of Toshiba TC110G family ■ Densities up to 129,000 raw gates ■ Channelless “ sea of gates” architecture ■ 1.5 firn drawn CMOS technology, scalable to 1.0 /¿m

A138G2

Abstract: t166h TTL catalog binary counters with D-flip flop 2-bit adder layout ON48 nand gate layout Q6600C T175 AN14
Contextual Info: } /i i s 000966 PRELIMINAR rfm c . DEVICE SPECIFICATION A P P L IE D M IC R O C IR C U IT S C O R P O R A T IO N Q6000 SERIES CMOS GATE ARRAYS FEATURES^ TECHNOLOGY _ Q6000 series arrays feature 2 ^ i l i c o n gate CMOS w ith 4wo^ level" metalizatiop? offering h ig n p e rfo rm a n c e and up to 85%

msm10t0209

Abstract: MSM10T0106 MSM10T0055 nor gate using TTL schematic diagram NAND gates MSM10T0416 4464 ram dc to ac 400 hz inverter collins MSM10T0262 1-INPUT NAND SCHMITT TRIGGER
Contextual Info: OKI_ January 1990 Preliminary Semiconductor_ MSM10T0000 1.0|im SEA-OF-GATES FAMILY GENERAL DESCRIPTION FEATURES Oki's MSM10T0000 Sea-of-Gates family is a performance enhanced, high-density product constructed from Oki's advanced 1.0|im drawn 0.85nm

RS flip flop IC

Abstract: internal structure of ic 4017 RS FLIP FLOP LAYOUT hc 7400 sentry 4017 equivalent toggle type flip flop ic
Contextual Info: MMMHS MA GATE ARRAY SERIES 3/J1 METAL LAYER ANATRA-HARRIS SEM ICO NDUCTO R MA 0250-MA 0400 MA 0800-MA 1200 JANUARY 1986 Features Description • HIGH SPEED CMOS : 2 NS/GATE TYPICAL PROPAGATION DELAY. • LOW CONSUMPTION : - STAND BY CURRENT 10 nA/GATE - OPERATING CURRENT