TPHL10 Search Results

Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590 – DECEMBER 1997 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps

Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442C – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC

CDC318

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

UT54AC

Contextual Info: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March 14, 2007 www.aeroflex.com/radhard FEATURES PIN DESCRIPTION ‰ Latchable transceiver with output source/sink of 24mA ‰ Option to select generate parity and check or "feed-through"

CDC319

Abstract: CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

CDC319

Abstract: MO-150
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

Contextual Info: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

48-PIN

Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

CDC2351

Abstract: CDC2351DB CDC2351DBG4 CDC2351DBLE CDC2351DBR CDC2351DBRG4 CDC2351Q
Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC

CDC351

Contextual Info: CDC351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS441C – FEBUARY 1994 – REVISED NOVEMBER 1995 D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC

K3638

Abstract: 4Y04
Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications

Contextual Info: CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS www.ti.com SCAS441D – FEBRUARY 1994 – REVISED OCTOBER 2003 FEATURES • DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications

Contextual Info: CDC2351ĆEP 1ĆLINE TO 10ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SGLS248A − JUNE 2004 − REVISED AUGUST 2004 D Controlled Baseline D D D D D D D D D D Outputs Have Internal Series Damping − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

CDC2351

Abstract: CDC2351MDBREP MO-150
Contextual Info: CDC2351ĆEP 1ĆLINE TO 10ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SGLS248A − JUNE 2004 − REVISED AUGUST 2004 D Controlled Baseline D D D D D D D D D D Outputs Have Internal Series Damping − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: PCK351 1:10 clock distribution device with 3-State outputs Rev. 01 — 14 May 2002 Product data 1. Description The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The PCK351 enables a single clock input to be distributed to ten outputs with minimum

Contextual Info: CDC2351ĆEP 1ĆLINE TO 10ĆLINE CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SGLS248A − JUNE 2004 − REVISED AUGUST 2004 D Controlled Baseline D D D D D D D D D D Outputs Have Internal Series Damping − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

CDC330

Contextual Info: CDC330 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS329A – OCTOBER 1993 – REVISED MARCH 1994 • • • • • • • • • DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs

Contextual Info: Standard Products UT54ACTS899 RadHard 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet March, 2009 www.aeroflex.com/Logic FEATURES PIN DESCRIPTION ‰ Latchable transceiver with output source/sink of 24mA ‰ Option to select generate parity and check or "feed-through"

CDC2351

Abstract: CDC2351DB CDC2351DBG4 CDC2351DBLE CDC2351DBR CDC2351DBRG4 CDC2351Q
Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC

48-PIN

Abstract: CDC318A
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications

CDC2351PWRG4

Abstract: CDC2351 CDC2351DB CDC2351DBG4 CDC2351DBLE CDC2351DBR CDC2351DBRG4 CDC2351Q
Contextual Info: CDC2351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442D – FEBRUARY 1994 – REVISED SEPTEMBER 2000 D D D D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC

54ALS161

Contextual Info: REVISIONS C Change VJL, tp clock , fflAX, and propagation delay limits. Delete minimum limits from IJL and propagation delays. Convert to military drawing format. Case E inactive for new design D Change drawing CAGE number to 67268. Change IJL condition. Change tpLH2 - Correct vendor p/n. Case 2, device types 01 and

MO-150

Abstract: CDC319
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590 – DECEMBER 1997 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps