TTL 4000 Search Results

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

F240 transistor

Abstract: TTL LS 7400 Transistor F240 LS00 from Motorola 12MRM IC TTL 7400 propagation delay LS TTL family characteristics 7400 TTL ls 7400 LS00
Contextual Info: Circuit Characteristics FAST AND LS TTL 2 CIRCUIT CHARACTERISTICS FAMILY CHARACTERISTICS LS TTL The Low Power Schottky LSTTL family combines a current and power reduction improvement over standard 7400 TTL by a factor of 5. This is accomplished by using Schottky diode clamping to prevent saturation and advanced processing.

Contextual Info: 8T30 N,F DESCRIPTION PIN CONFIGURATION The 8T30 is a dual bi-directional bus interchange element that interfaces MOS and TTL data busses. Data can be exchanged in a half-duplex transmission mode from a “ party line” TTL/DTL bus to a MOS transceiver port and a TTL/DTL transceiver port.

Contextual Info: ME RR IM AC INDUSTRIES INC i<bE D • b 0 0 4 b 3 R DDDlRflS T ■ M H I I M Merrimac b tf -2a series TTL Bl PHASE MODULATORS Integral Fact TTL Drivers Fast Switching Speed • • • • 10 MHz to 1000 MHz Frequency Range Direct TTL Compatible Input Space Saving Hermetic Design

8-pin 3773

Abstract: 100ELT21 3773
Contextual Info: SK10/100ELT21W Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100ELT21W is a single differential PECL to CMOS/TTL Translator. Since PECL Positive ECL levels are used, only +VCC and ground are required.

Contextual Info: National Semiconductor 54F/74F132 Quad 2-Input NAND Schmitt Trigger General Description The ’F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing

Contextual Info: & National Semiconductor 54F/74F132 Quad 2-lnput NAND Schmitt Trigger General Description The 'F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing

diagram of hi 3520

Abstract: SK100ELT21W SK100ELT21WD SK100ELT21WDT SK10ELT21W SK10ELT21WD SK10ELT21WDT 100LVELT21
Contextual Info: SK10/100ELT21W Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100ELT21W is a single differential PECL to CMOS/TTL Translator. Since PECL Positive ECL levels are used, only +VCC and ground are required.

MC100ELT23

Abstract: MC100LVELT23 SK100ELT23W SK100ELT23WD SK100ELT23WDT SK100ELT23WU
Contextual Info: SK100ELT23W Dual Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK100ELT23W is a dual differential PECL to CMOS/TTL or LVCMOS/LVTTL Translator. Since PECL Positive ECL levels are used, only positive VCC and

Contextual Info: SK100ELT23W Dual Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK100ELT23W is a dual differential PECL to CMOS/TTL or LVCMOS/LVTTL Translator. Since PECL Positive ECL levels are used, only positive VCC and

74f132 national

Abstract: 54F132DM 54F132FM 54F132LM 74F132PC F132 J14A M14A M14D N14A
Contextual Info: General Description The ’F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In

signal path designer

Contextual Info: PRELIMINARY DEVICE SPECIFICATION Q20000 SERIES ECL/TTL TURBO" LOGIC ARRAYS 020000 FEATURES • Up to 24000 gates, channelless architecture • 100ps equivalent gate delays • Ultra low power ,5-1.0mW/gate • 10K, 10KH, 100K ECL and mixed ECL/TTL capability

TTL DIODE

Abstract: TTL catalog
Contextual Info: Extract from the online catalog SIM-EI- 12DC/TTL/100 Order No.: 2271141 The illustration shows version SIM-EI- 5DC/TTL/100 Input optocoupler, with protection circuits in input and output circuits,

Contextual Info: Extract from the online catalog SIM-EI- 24DC/TTL/100 Order No.: 2271154 The illustration shows version SIM-EI- 5DC/TTL/100 Input optocoupler, with protection circuits in input and output circuits,

100ELT25

Contextual Info: SK10/100ELT25W Differential ECL to TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features • The SK10/100ELT25W is a differential ECL to TTL translator. Because ECL levels are used, a +5.5V / +3.0V, –5.5V / –3.0V, and ground supplies are required. The SK10/

Contextual Info: Extract from the online catalog SIM-EI- 12DC/TTL/100 Order No.: 2271141 The illustration shows version SIM-EI- 5DC/TTL/100 Input optocoupler, with protection circuits in input and output circuits,

cmos logic 4000 series

Abstract: H3064 HS-150 Series NEL Frequency Controls
Contextual Info: NEL ' T r ^ 0 - 'Z 3 > Crystal Clock Oscillator HS-150 Series TTL HS-360 Series (CMOS) 63.0 MHz - 200.0 MHz Description Suggested Applications The HS-150 Series of quartz crystal clock oscillators are general purpose, TTL and STTL compatible oscillators.

Contextual Info: Extract from the online catalog SIM-EI- 24DC/TTL/100 Order No.: 2271154 The illustration shows version SIM-EI- 5DC/TTL/100 Input optocoupler, with protection circuits in input and output circuits,

TTL DIODE

Contextual Info: Extract from the online catalog SIM-EI- 24DC/TTL/100 Order No.: 2271154 The illustration shows version SIM-EI- 5DC/TTL/100 Input optocoupler, with protection circuits in input and output circuits,

MC100ELT23

Abstract: MC100LVELT23 SK100ELT23W SK100ELT23WD SK100ELT23WDT SK100ELT23WU pin diagram of 3525
Contextual Info: SK100ELT23W Dual Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator HIGH-PERFORMANCE PRODUCTS Description Features The SK100ELT23W is a dual differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator. Since PECL Positive ECL levels are used, only positive

Contextual Info: Extract from the online catalog SIM-EI- 5DC/TTL/100 Order No.: 2271138 Input optocoupler, with protection circuits in input and output circuits, input: 5 V DC, output: TTL logic level, max. 100 mA

Contextual Info: S3 National ÆÆ Semiconductor 54F/74F13 Dual 4-Input NAND Schmitt Trigger General Description The 'F13 contains two 4-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing

C2083

Abstract: CMOS 4000 specifications AT90-0107 AT90-0107-TB AT90-0107TR
Contextual Info: AT90-0107 Digital Attenuator, 31.5 dB, 6-Bit, TTL Driver, DC-4.0 GHz CSP-1 Features ! ! ! ! ! ! ! V 7.00 Attenuation: 0.5 dB Steps to 31.5 dB Low DC Power Consumption Small Footprint, JEDEC Package Integral TTL Driver 50 ohm Impedance Test Boards are Available

MC100ELT24

Abstract: SK100ELT24W SK100ELT24WD SK100ELT24WDT SK100ELT24WMS
Contextual Info: SK100ELT24W TTL to Differential ECL Translator HIGH-PERFORMANCE PRODUCTS Description Features • The SK100ELT24W is a single TTL to Differential ECL translator. Because ECL levels are used, a +3.3/ 5.0V, -3.3/–5.0V and ground power supplies are required. The SK100ELT24 is functionally compatible