TTL 74LS137 Search Results

74LS08 fan-in

Abstract: 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245
Contextual Info: Selection Information FAST/LS TTL 1 Circuit Characteristics 2 Design Considerations, Testing and Applications Assistance Form 3 FAST Data Sheets 4 LS Data Sheets 5 Reliability Data 6 Package Information Including Surface Mount 7 FAST AND LS TTL DATA CLASSIFICATION

74LS82

Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
Contextual Info: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC

HC137

Abstract: M54HCT137 M54HCT137F1R M74HCT137 M74HCT137B1R M74HCT137C1R M74HCT137M1R
Contextual Info: M54HCT137 M74HCT137 3 TO 8 LINE DECODER/LATCH INVERTING . . . . . . . HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE CAPABILITY

Y4 diode

Abstract: TC74HCT137
Contextual Info: TC74HCT137P/F TC74HCT137P/F 3-T0-8 LINE DECODER/LATCH The TC74HCT137 is a high speed CMOS 3-TO-8 LINE DECODER ADDRESS LATCH fabricated with silicon gate C2M0S technology. This device may be used as a level converter for interfacing TTL or NMOS to High Speed

g1g7

Abstract: M74HCT13
Contextual Info: r z 7 SCS-THOM SON Ä 7 # [»imeglTIFMOOS M54HCT137 M74HCT137 3 TO 8 LINE DECODER/LATCH INVERTING • HIGH SPEED tPD = 17 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 pA (MAX.) AT T a = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS Vih = 2V (MIN.) V il = 0.8V (MAX)

137C1

Contextual Info: r r 7 ^ 7 # S G S -T H O M S O N IM D S i« ! » « ! ms4HCT137 M 7 4 H C T 1 37 3 TO 8 LINE DECODER/LATCH INVERTING • HIG HSPEED tpD = 17 ns (TYP.) AT Vcc = 5 V . LOW POWER DISSIPATION Ice = 4 fiA (MAX.) AT TA = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS

Contextual Info: r r r s g s -t h o m s o n ms4h c t i 37 M 74HCT137 M ffls J im g T M K S 3 TO 8 LINE DECODER/LATCH INVERTING • HIGHSPEED tpD = 17 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 hA (MAX.) AT Ta = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN.) V il = 0.8V (MAX)

74LS137

Abstract: SN54LSXXXJ SN74LSXXXD SN74LSXXXN M 5229 751B-03
Contextual Info: SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 16 15 14 13 12 11 10 9 Y0 Y1 Y2 Y3 Y4 Y5 C GL G2 G1 Y6 Y7 A B

74LS137

Abstract: aag2
Contextual Info: <8> M O TO R O LA SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC YÛ Y1 Y2 Y3 Y4 Y5 Y6 pisi |~i?1 |~ÌT| HT! fiil f~M~| [~iÖ1 [~9~|

ic 74ls137

Abstract: 74ls137
Contextual Info: MOTOROLA SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS V cc YO Y1 Y2 Y3 Y4 Y5 Y4 Y5 Y6 Y ï T T ; Y0 Y1 Y2 Y3 A J SUFFIX C E R A M IC

74LS137

Abstract: 16y0y1 SN54LSXXXJ SN74LSXXXD SN74LSXXXN Y4 DIODE TTL 74ls137 diode high voltage Y5
Contextual Info: SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC 16 Y0 Y1 Y2 Y3 Y4 Y5 Y6 15 14 13 12 11 10 9 Y0 Y1 Y2 Y3 Y4 Y5 C GL G2 G1 Y6 Y7 A B

74LS137

Contextual Info: <8> MOTOROLA SN54/74LS137 D A T A O U T PU T S V CC / Y0 Y1 f61 £¡1 Fyi YO Y2 Y3 Y4 FI R I YS Y6 ^ FH R Y1 Y2 Y3 Y4 Y5 C GL 53 GJ Y7 A fT | 3-UNE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES Y6 B TTTTTT “ V" SELECT Cy x 6 l 53 G îy LOW POWER SC HO TTK Y

74LS137

Abstract: SP74SC137F SP74SC137N
Contextual Info: SP7 4 S C 1 3 7 S DECODER/DEMULTIPLEXER P I PIN CONFIGURATIO N FEATURES C • Designed for high performance memory decoders in microprocesor systems ■ 3 to 8 line decoders 3 enable inputs and inverted outputs with latches ■ Pin com patible with 74LS137

logos 4012B

Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
Contextual Info: L p i > « , * S E m Ic O N VOLUM E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 5th EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY S E M IC O N IN D E X E S L IM IT E D THE SEMICON INDEX SERIES CONSISTS OF VOLUME 1 TRANSISTOR INDEX VOLUME 2 DIODE & SCR INDEX

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 4 BIT COUNTER 74669 la 4508 ic schematic diagram XF107 74295 random number generator by using ic 4011 and 4017
Contextual Info: General Features The SCxD4 series of high performance CMOS gate arrays offers the user the ability to realise customised VLSI inte­ grated circuits featuring the speed performance previously obtainable only with bipolar technologies whilst retaining all the advantages of CMOS technology; low power consum p­

Contextual Info: SN54LS137, SN74LS137 3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS 0 24 16 . JUN E 197 8-R EV 1S ED • Com bines Decoder and 3-Bit Address Latch I I • Incorporates 2 Enable Inputs to Simplify Cascading A C B C I • Low Power Dissipation . . . 65 mW Typ

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder data sheet ic 74139 Quad 2 input nand gate cd 4093
Contextual Info: General Features The SCxD4 series of high perform ance CM O S gate arrays offers the user the ability to realise custom ised VLSI inte­ grated circuits featuring the speed perform ance previously obtainable only with bipo lar tech nolog ies whilst retaining all

54LS137

Abstract: 74LS137 Y561
Contextual Info: SN 54LS137, SN74LS137 3-LINE TO 8-LINE DECODERS/DEM ULTIPLEXERS W IT H ADDRESS LATCHES _ • Com bines D eco der and 3-Bit Address Latch • Incorporates 2 Enable Inputs to Sim plify Cascading • D 2 4 1 6 , J U N E 1 9 7 6 — R E V IS E D M A R C H

74LS137

Contextual Info: MOTOROLA SN54LS137 SN74LS137 D ATA OUTPUTS VCC / YQ Yt YZ V3 Y4 Y6 Y6 ^ Fel [Tsl F^l [Til [Tzl [7Ï1 Fpl f a l VO Y1 Y2 Y3 Y4 Y5 C SL GS G1 Y7 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY t ï I T inmunii lij til ili l±j

74LS137

Contextual Info: MOTOROLA < 8 > V CC D A T A O U TP U TS _ A _ Y3 Y4 / Y0 Y1 Y2 YO Y1 Y2 Y3 SN54LS137 SN74LS137 Y5 Y4 Y6 N 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES Y5 TTTT LOW POWER SCHOTTKY LU LU üJ'Lll Li] LU, LzJ l£j , A B 'V ” C / VGL S I V" G1

toshiba tc110g

Abstract: 74LS82 74ls150 74LS514 toshiba tc140g 74ls150 pin configuration 74LS273 SC11C1 diode sr45 74LS194 internal circuit diagram
Contextual Info: SIEMENS AKTIEN6ESELLSCHAF 47E » • BS3SbOS 0037405 7 » S I E G General Description Our Sea-of-Gates concept is based on a highperformance CMOS technology, in either 1.5 micron or 1.0 micron transistor gate length. This is equivalent to 1.1 or 0.8 micron effective

ic 74ls137

Contextual Info: TC74HCT137AP/AF 3-TO-8 LINE DECODER/LATCH The TC74HCT137A is a high speed CMOS 3 -to -8 LINE DECODER ADDRESS LATCH fabricated with silicon gate C!MOS technology. It achieves the high speed operation sim ilar to equivalent LSTTL while m aintaining the CMOS low power

Contextual Info: TC74HCT137AP/AF 3 - T O - 8 L IN E D E C O D E R / L A T C H The TC74HCT137A is a high speed CMOS 3 - to - 8 LIN E D EC O D ER A D D R E SS LA TCH fab ricated w ith silicon gate C2MOS technology. It achieves the high speed operation s im ila r to equivalent LSTTL w hile m ain tain in g the CMOS low pow er

dinverter 768r

Abstract: G7D-412S Ericsson Installation guide for RBS 6201 OMRON G7d TH3 thermistor 6201 RBS ericsson user manual TMS77C82NL reed relay rs 349-355 i ball 450 watt smps repairing RBS -ericsson 6601
Contextual Info: Discontinued and Superseded Stock Number History. This document contains Discontinued and Superseded Stock Number History. The information is listed in the following format: Stock Number: The original RS Stock Number of the item. Brief Description: The Invoice Description of the item.