U 8000 BGA Search Results

8DDD

Abstract: 8282
Contextual Info: FLEX 8000 Programmable Logic Device Family J u n e 1996, ver. 8 Features. D ata S h ee t • ■ ■ ■ Table 1. FLEX 8000 Device Features Feature U sable gates Flipflops Logic array blocks LABs Logic elem ents M axim um user I/O pins JTA G B S T circuitry

Contextual Info: FLEX 8000 M U S S Programmable Logic Device Family , June 1996, ver. 8 Features. Data Sheet • ■ ■ ■ Table 1. FLEX 8000 Device Features Feature EPF8282A EPF8282AV EPF8452A EPF8636A 2,500 4,000 6,000 8,000 12,000 16,000 282 452 636 820 1,188 1,500

f8452

Abstract: EPF8820A
Contextual Info: F L E X 8000 Æ G Ü I S & Programmable Logic Device Family . J a n u a ry 1998. ver, S Features. Data Sheet • ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS program m able logic device PLD family (see Table 1) 2,500 to 16,000 usable gates

pf815

Abstract: sim 300 v 703 p10n10
Contextual Info: F L E X 8000 Programmable Logic Device Family J a n u a r y 1 9 9 8 . v e r. 9 Features. D a ta S h e e t • ■ ■ ■ ■ Low -cost, high-density, register-rich CMOS p ro gram m able logic device PLD fam ily (see Table 1) 2,500 to 16,000 usable gates

Contextual Info: TMX320C6201 DIGITAL SIGNAL PROCESSOR SPRS051B - JANUARY 1997 - REVISED JUNE 1997 Highest Performance Fixed-Point Digital Signal Processor DSP : GGP 352-PIN BGA PACKAGE (BO TTO M V IE W ) I 26 o o o o o o o o o o o o o o o o o o o o o o o o o o - 1 600 MIPS @ 200 MHz

TQFP 100 PACKAGE footprint

Abstract: 225-pin BGA transistor BF 998 BGA and QFP Package PQFP ALTERA 160 PLCC pin configuration 84 pin plcc ic base 2030 ic 5 pins 256-pin BGA AW 55 IC
Contextual Info: Packaging Solutions Advanced Packaging Solutions for High-Density PLDs June 1998 • package options • pin compatibility Advanced • design flexibility Packaging Solutions FineLine BGA • vertical migration • space efficiency • cost-effectiveness

Contextual Info: M UM FLEX 8000 Programmable Logic Device Family June 1999, ver. 10. Features. • ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS p ro g ram m ab le logic device PLD fam ily (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System -level features

EFP8636A

Abstract: 00D47 N1137 FLEX 8000 family 5T53 u16203 129f17
Contextual Info: FLE X 8000 Programmable Logic Device Family June 1996, ver. 8 Features. Data Sheet • ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS p rogram m able logic device fam ily see Table 1 2,500 to 16,000 usable gates 282 to 1,500 registers System -level features

Contextual Info: FLEX 8000 Programmable Logic Device Family January 1998. ver. 9 Features. Data Sheet • ■ ■ ■ Low-cost, high-density, register-rich CMOS program m able logic device PLD family (see T a b l e 1) 2,500 to 16,000 usable gates 282 to 1,500 registers

AXP 188 IC

Abstract: AXP 192
Contextual Info: Includes FLEX 8000 H a w * /an q rs r*a \ Programmable Logic Device Family Data Sheet August 1994, ver. 4 Features □ □ □ □ □ □ □ □ □ □ □ □ H igh-density, register-rich program m able logic device fam ily 2,500 to 16,000 usable gates

SCC68070

Abstract: ci cd 4058 Z807 SOT220 SCR SN 101 SCC68070CCA84 crystal oscillator marking 400d SCC68070ACA84 SCC68070CBB 68440
Contextual Info: NOV 2 6 1990 Philips Components Data sheet status P r o d u c t s p e c ific a tio n date of issue N o v e m b e r 1990 SCC68070 16/32-bit microprocessor FEATURES • C M O S technology l% f o JJ J ILn • 32-bit internal structure • Enhanced bus error handling

Contextual Info: FLEX 8000 Programmable Logic Device Family M a y 1 8 8 3 . ve r. 9.1 n Features. D a te S h e e t 888 SIS 888 88 Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers

Contextual Info: FLEX 8000 Programmable Logic Device Family Data Sheet Features. • ■ ■ ■ Low-cost, high-density, register-rich CMOS program m able logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features

epf8282 hardware

Abstract: epf8282 block pf815 EPF81188 PF8150 EPF8282
Contextual Info: FLEX 8000 Programmable Logic Device Family Datasheet August 1993, ver. 3 Features □ □ □ □ □ □ □ □ □ □ □ □ High-density, register-rich programmable logic device family 2,500 to 24,000 usable gates 282 to 2,252 registers Fabricated on a 0.8-m icron CM OS SRAM technology

N1137

Contextual Info: FLEX 8000 • fa Programmable Logic Device Family m Features. ■ ■ ■ ■ ■ Low-cost, high-density, register-rich CM OS program m able logic device PLD fam ily (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features

Contextual Info: FLEX 8000 Programmable Logic Device Family S e p te m b e r 1S9S» v e r. 9.11 Features. D ata S h e e t Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see T;?bie 1) 2,500 to 16,000 usable gates 282 to 1,500 registers

programming manual EPLD EPS448

Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Contextual Info: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,

Contextual Info: FLEX 8000 Programmable Logic Device Family May 1999, ver. 10 Features. D a ta she et • ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features

EPF8820

Contextual Info: Includes FLEX8000A FLE X 8000 OUUU Programmable Logic Device Family March 1995, ver. 6 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device family 2,500 to 16,000 usable gates 282 to 1,500 registers see Table 1

EPF8282

Contextual Info: FLE X 8000 Includes FLEX 8000A • OUUU Programmable Logic Device Family March 1995, ver. 6 Features. Data Sheet ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device family 2,500 to 16,000 usable gates

k0215

Abstract: 128MX8 240-PIN PC2-5300 PC2-6400 vl393t5663a-e7
Contextual Info: Product Specifications PART NO: REV: 1.0 VL393T5663A-E7/E6 General Information 2GB 256Mx72 DDR2 REGISTERED ECC 240 PIN DIMM Description: The VL393T5663A is a 256Mx72 DDR2 SDRAM high density DIMM. This memory module consists of eighteen CMOS 128MX8 bit with 8 banks DDR2 Synchronous DRAMs in BGA packages, two 25-bit Registered buffers,

PLE3-12 EP1810

Contextual Info: ÆoniM Glossary June 1996 A Altera Hardware Description Language AHDL A ltera's design entry language. AHDL is a highlevel, modular language that is com pletely integrated into M A X +P L U SII. You can create AHDL Text Design Files (.tdf) with the M A X+PLUS II Text Editor or any standard text

altera jed to pof convert

Abstract: EP1810 jedec EPM memory epx780 ep330
Contextual Info: / a \| l l l" £ Glossary March 1995 A Altera Hardware Description Language AHDL A ltera's design entry language. AH DL is com pletely integrated into M A X +P L U S II, and allows the designer to enter and edit Text Design Files (.tdf) with the M A X +PLU S II Text

Philips PE 1213

Abstract: SCC68070 SSW-9 BCD to Seven Segment 4055 meab 8046 microprocessor block diagram and pin diagram xtal mco 8059 SCR112 MSR14 scc68
Contextual Info: MAY 2-6 M3 INTEGRATED CIRCUITS SCC68070 16/32-bit microprocessor Product specification File under Integrated Circuits, IC21 April 1993 Philips Semiconductors PHILIPS PHILIPS Philips Semiconductors Product specification 16/32-bit microprocessor SCC68070 CONTENTS