ULTRA39192 Search Results

ULTRA39192 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
ltra Contextual Info: ^ CYPRESS ADVANCED INFORMATION Ultra39192 UltraLogic 192-Macrocell CPLD Features F unctional D escription • 192 m acrocells in 12 logic blocks • In-S ystem R ep rogram m ab le ISR • Fully PCI com p liant T h e U ltra 3 9 1 9 2 is a h igh*density, hig h p e rfo rm a n c e C o m p le x P ro g ra m m a b le	OCR Scan	160-pin ltra39256 Ultra39192 192-Macrocell ltra	PDF
ultra39000 Contextual Info: 7C39192: August 7, 1995 Revised: October 9, 1995 ADVANCED INFORMATION Ultra39192 UltraLogict 192ĆMacrocell CPLD Features D D D D D D D D D D 192 macrocells in 12 logic blocks InĆSystem Reprogrammable ISRt Fully PCI compliant Full JTAG compatability 3.3V or 5V operation	Original	7C39192: Ultra39192 192Macrocell Ultra39000 Ultra39192	PDF
22V10s Abstract: 7C39256 ultra39000 Contextual Info: 7C39256: August 4, 1995 Revision: October 9, 1995 ADVANCED INFORMATION Ultra39256 UltraLogict 256ĆMacrocell CPLD Features D D D D D D D D D D Functional Description 256 macrocells in 16 logic blocks InĆSystem Reprogrammable ISRt Fully PCI compliant Full JTAG compatibility	Original	7C39256: Ultra39256 256Macrocell 160pin 208pin Ultra39192 Ultra39320 Ultra39256 22V10s 7C39256 ultra39000	PDF
ALI chipset Ali 3516 Abstract: SEM 2006 6216 static ram sem 2005 ALI chipset Ali 3510 vl82c483 ali 3516 CMOS 5408 PAL Decoder 16L8 1K x 8 static ram Contextual Info: June 1996 Cypres Semiconductor Corporation NUMERIC DEVICE INDEX Document Number Device Number 5000 5000 3518 3518 3519 CY101E383 CY10E383 CY2071 CY2081 CY2250 3522 3509 CY2252 CY2254A 3510 CY2255 3517 CY2257 3520 CY2260 3511 3023 3024 3011 3013 3019 3006 3023	Original	CY101E383 CY10E383 CY2071 CY2081 CY2250 CY2252 CY2254A CY2255 CY2257 CY2260 ALI chipset Ali 3516 SEM 2006 6216 static ram sem 2005 ALI chipset Ali 3510 vl82c483 ali 3516 CMOS 5408 PAL Decoder 16L8 1K x 8 static ram	PDF
vhdl synchronous bus Abstract: thesis IEEE1164 ultra39000 Contextual Info: 7C3900: August 30, 1995 Revised: October 9, 1995 ADVANCED INFORMATION Features High density D High performance Ċ 192-512 macrocells Ċ 64-224 I/O pins Ċ Multiple input/clock pins Ċ 125-100 MHz performance Ċ 10-12 ns t Ċ 5-6 ns t Ċ 5.5-6.5 ns t PD S D	Original	7C3900: Ultra39000, vhdl synchronous bus thesis IEEE1164 ultra39000	PDF