USE PRESET 100K Search Results

7b45

Abstract: schematic diagram of phone charger sot-23 marking YA Lithium-Ion Battery Charger sot 23 mark py sot IRF7805 SC1437 2sc1437 SOT23-5 marking par
Contextual Info: SC1437 Precision Voltage Detector With Programmable Trigger Voltage & Timer Delay POWER MANAGEMENT Description Features Low quiescent current, less than 10µA typical Input voltage range 1.8V to 6.8V Adjustable or preset voltage trip point Selectable timer delays of 0, 40 and 80ms without use of

0-15 minutes timer

Abstract: 50hz bcd clock minutes seconds 50hz 100hz generator 24hr clock circuit KKA8583N alarm clock IC circuit of alarm clock
Contextual Info: TECHNICAL DATA CMOS timer with RAM and I2C-bus control. KKA8583N KKA8583N is a timer with RAM and I2C-bus control. Designed for use in appliances having I2C-bus as clock/calendar/timer/alarm/events counter for turning on functions of the appliance at preset time or upon completion of an

INA8583

Abstract: Ina8583n 50hz 100hz generator alarm clock by ic oscillator 32,768KHz 5V alarm clock IC
Contextual Info: TECHNICAL DATA CMOS timer with RAM and I2C-bus control. INA8583N INA8583N is a timer with RAM and I2C-bus control. Designed for use in appliances having I2C-bus as clock/calendar/timer/alarm/events counter for turning on functions of the appliance at preset time or upon completion of an

MAX843

Contextual Info: 19-0388; Rev 0; 4/95 V M y J X IV M Low-Noise, Regulated, -2V GaAsFET Bias The MAX840 offers both a -2V preset output and a -0.5V to -9.4V a d ju stab le output. The M AX843/M AX844 use an external positive control voltage to set the negative output voltage. Input voltage range for all the devices is

WIDE BUS FAMILY

Contextual Info: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 15K to 100K usable gates — 256 to 1536 macrocells — 92 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global control signal pins; 4 JTAG interface pins for

Contextual Info: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global I/O control signal pins; 4 JTAG interface pins

Contextual Info: ISL45024 Data Sheet January 2004 256-Tap Quad-Channel Non-Volatile Digital Potentiometer FN6070 Features • 256 taps for each potentiometer The ISL45024 is a 256-tap, quad-channel non-volatile digital potentiometer available in 10kΩ, 50kΩ and 100kΩ end-to-end

Contextual Info: ISL45024 Data Sheet 256-Tap Quad-Channel Non-Volatile Digital Potentiometer The iPot ISL45024 DCP is a 256-tap, quad-channel non-volatile digital potentiometer available in 10kΩ, 50kΩ and 100kΩ end-to-end resistances. These devices can be used

AEH 5PIN

Abstract: MAX8510 MAX8511 MAX8512 MAX8512EXK-T SC70-5
Contextual Info: 19-2732; Rev 0; 1/03 KIT ATION EVALU LE B A IL A AV Ultra-Low-Noise, High PSRR, Low-Dropout,120mA Linear Regulators in SC70 Features ♦ Space-Saving 5-Pin SC70 Package ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth MAX8510 ♦ 78dB PSRR at 1kHz (MAX8510)

F100K

Abstract: SY100S336 SY100S336A SY100S336AFC SY100S336AJC SY100S336AJCTR
Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1100ps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ IEE min. of –170mA ■ Industry standard 100K ECL levels

Contextual Info: / T u TECHNOLOGY r m _LT1176/LT1176-5 Step-Down Switching Regulator FCRTURCS tion. The power switch, all oscillator and control circuitry, • 1,2A On-Board Switch ■ 100kHz Switching Frequency The topology is a classic positive “buck” configuration but

SY100S336

Abstract: SY100S336A SY100S336AFC SY100S336AJC SY100S336AJCTR F100K
Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER FEATURES DESCRIPTION • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 1100ps ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50% ■ IEE min. of –170mA ■ Industry standard 100K ECL levels

MAX8510

Abstract: MAX8511 MAX8512 SC70-5 AEH 5PIN amplifier - ATH top mark
Contextual Info: 19-2732; Rev 4; 8/11 Ultra-Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulators Features ♦ Space-Saving SC70 and TDFN 2mm x 2mm Packages ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth (MAX8510) ♦ 78dB PSRR at 1kHz (MAX8510) ♦ 120mV Dropout at 120mA Load

38K30

Abstract: DELTA39K
Contextual Info: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and

38K30

Abstract: DELTA39K CY3LV010
Contextual Info: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and

MAX8510

Abstract: MAX8511 MAX8512 SC70-5
Contextual Info: 19-2732; Rev 3; 5/06 Ultra-Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulators Features ♦ Space-Saving SC70 and TDFN 2mm x 2mm Packages ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth (MAX8510) ♦ 78dB PSRR at 1kHz (MAX8510) ♦ 120mV Dropout at 120mA Load

100K preset horizontal

Abstract: LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510
Contextual Info: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan

Contextual Info: 19-4662; Rev 0; 6/09 Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulator Features ♦ Space-Saving SC70 ♦ 25µVRMS Output Noise at 100Hz to 100kHz Bandwidth ♦ 65dB PSRR at 10kHz ♦ 120mV Dropout at 120mA Load ♦ Stable with 1µF Ceramic Capacitor for Any Load

Contextual Info: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG

preset resistor 10k

Abstract: 4.7k Preset preset 10k preset resistor preset 10k ohm 2.2k Preset 10K preset PRESET 10K DATASHEET relay,10A data sheet of preset 10k
Contextual Info: KEPTROL Counter, Timer or Ratemeter Features • Counter, Timer or Ratemeter • Counts Up To 100 kHz PRESET COUNTERS • 8 Digit Display • Input Scaling • Batch Counter • DC Output to Power Peripherals Sensors • NEMA 4X / IP65 Sealed Front Panel Applications:

208EQFP

Contextual Info: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG

MAX8940

Contextual Info: 19-4662; Rev 0; 6/09 Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulator Features ♦ Space-Saving SC70 ♦ 25µVRMS Output Noise at 100Hz to 100kHz Bandwidth ♦ ♦ ♦ ♦ ♦ 65dB PSRR at 10kHz 120mV Dropout at 120mA Load Stable with 1µF Ceramic Capacitor for Any Load

mark X51

Abstract: aar transistor
Contextual Info: 19-2732; Rev 3; 5/06 Ultra-Low-Noise, High PSRR, Low-Dropout, 120mA Linear Regulators Features ♦ Space-Saving SC70 and TDFN 2mm x 2mm Packages ♦ 11µVRMS Output Noise at 100Hz to 100kHz Bandwidth (MAX8510) ♦ 78dB PSRR at 1kHz (MAX8510) ♦ 120mV Dropout at 120mA Load

Contextual Info: 19-2662; Rev 0; 10/02 High-Efficiency, Triple-Output, Keep-Alive Power Supply for Notebook Computers Features The MAX1534 is a high-efficiency, triple-output power supply for keep-alive always on voltage rails. The 500mA buck regulator with an internal current-limited