VCXO 2048 KHZ Search Results

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45A MK2069 MT9045 TR62411 crystal 27 MHz
Contextual Info: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input

Contextual Info: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 MK2049-45A MT9045 TR62411
Contextual Info: DATASHEET MK2049-45 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input

MK2049-45A

Abstract: MT9045 TR62411 ETS300 GR-1244 MAN05 MK2049-34 MK2049-36 MK2069 FXP MARKING
Contextual Info: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input

Contextual Info: DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-45 Description Features The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input

MK2049-45ASILFTR

Abstract: ETS300 GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45A MT9045 TR62411 vcxo 2048 khz
Contextual Info: DATASHEET MK2049-45A 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input

MAN05

Abstract: MK2049-34 MK2049-36 MK2049-36SI MK2049-45 TR62411 ETS300 GR-1244
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

Contextual Info: DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL M K 2 0 4 9 -3 6 Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

ETS300

Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-36SI MK2049-36SITR MK2049-45 TR62411 MK2049-36SILF
Contextual Info: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications

Contextual Info: MK2049-45A 3.3 Volt Communications Clock PLL Description Features The MK2049-45A is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate

Contextual Info: MK2049-45 3.3V Communications Clock PLL Description Features The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate

Contextual Info: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate

Contextual Info: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate

Contextual Info: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate

HD-SDI over sdh

Abstract: stc crystal 6-SOT23 DS1080L DS1081L DS1083L DS1086 DS1086L DS1087L DS1089L
Contextual Info: System Timing & Control 8th Edition February 2009 Spread-spectrum clock modulators reduce peak EMI in LCD panels Pin-selectable dither rate and magnitude reduce radiated emissions by up to 17dB An integrated phase-locked loop PLL modulates the output clock around the center frequency at a pinselectable magnitude, thus reducing peak EMI at fundamental and harmonic frequencies. This is accomplished

Contextual Info: MK2049-45 3.3V Communications Clock PLL Description The MK2049-45 is a dual Phase-Locked Loop PLL device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate

Contextual Info: DATASHEET COMMUNICATIONS CLOCK JITTER ATTENUATOR MK2058-01 Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined

TXM TX 2E

Abstract: 59 PAA MS-026 S-PQFP-G100 TLV320AD13A
Contextual Info: TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE ADSL INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 – AUGUST 2000 D D D D D D Complete Discrete Multitone (DMT)-Based Asymmetric Digital Subscriber Line (ADSL) Coder/Decoder (Codec) Solution

TXM TX 2E

Abstract: VCXO 35.328MHz TNETD
Contextual Info: TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE ADSL INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 – AUGUST 2000 D D D D D D Complete Discrete Multitone (DMT)-Based Asymmetric Digital Subscriber Line (ADSL) Coder/Decoder (Codec) Solution

MAN05

Abstract: MK2058-01 MK2058-01SI MK2058-01SITR MT9045
Contextual Info: DATASHEET MK2058-01 COMMUNICATIONS CLOCK JITTER ATTENUATOR Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined

MK2058-01

Abstract: MAN05 MT9045 mk2058-01silf
Contextual Info: DATASHEET MK2058-01 COMMUNICATIONS CLOCK JITTER ATTENUATOR Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined

M540K

Abstract: MAN05 MK2058-01 MK2058-01SI MK2058-01SITR MT9045
Contextual Info: DATASHEET MK2058-01 COMMUNICATIONS CLOCK JITTER ATTENUATOR Description Features The MK2058-01 is a VCXO Voltage Controlled Crystal Oscillator based clock jitter attenuator designed for system clock distribution applications. This monolithic IC, combined