VEM GENERATOR Search Results

SN54FB2033

Abstract: SN74FB2033A
Contextual Info: SN54FB2033, SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVERS S C BS174G - N O VEM BER 1991 - REVISED N O VEM BER 1996 Compatible With IEEE 1194.1-1991 BTL Standard B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage

QS3245

Abstract: SN74CBT3245A
Contextual Info: SN74CBT3245A OCTAL BUS SWITCH SC DS002G - N O VEM BER 1992 - REVISED N O VEM BER 1996 • Functionally Equivalent to QS3245 • Standard ’245-Type Pinout DB, DGV, DW, O R PW PACKAGE TOP VIEW • 5 -il Switch Connection Between Two Ports • TTL-Compatible Control Input Levels

SN74FB2041A

Abstract: FB2041A SN54FB2041A 3a03
Contextual Info: SN54FB2041A, SN74FB2041A 7-BIT TTL/BTL TRANSCEIVERS S C B S 1 7 2 E - N O VEM BER 1991 - REVISED N O VEM BER 1996 Compatible With IEEE 1194.1-1991 BTL Standard B-Port Biasing Network Preconditions the Connector and PC Trace to the Backplane Transceiver Logic High-Level Voltage

SN54FB2032

Abstract: SN74FB2032
Contextual Info: SN54FB2032, SN74FB2032 9-BIT TTL/BTL COMPETITION TRANSCEIVERS S C B S 1 7 5 E - N O VEM BER 1991 - REVISED N O VEM BER 1996 • ■ • I I f Compatible With IEEE 1194.1-1991 BTL Standard • TTL A ^ o rt, Backplane Transceiver Logic (BTL) B Port • Open-Collector B-Port Outputs Sink

SN54FB2040

Abstract: FB2040 SN74FB2040
Contextual Info: SN54FB2040, SN74FB2040 8-BIT TTL/BTL TRANSCEIVERS S C B S 1 7 3 F - N O VEM BER 1991 - REVISED N O VEM BER 1996 C om patible W ith IEEE 1194.1-1991 BTL S tandard BIAS V c c Pin M inim izes S ignal D isto rtio n D uring Live Inse rtio n o r W ithdraw al TTL A J^ort, B ackplane T ra nsce ive r Lo g ic

Contextual Info: SN74LVCC4245A OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS _ SC AS5a4D^JO VEM M Hm 6-REVISEDD ECE^ER 1997 EPIC Enhanced-Performance Implanted CMOS Submicron Process V DB,

Contextual Info: SN54HCT32, SN74HCT32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS064A - NO VEM BER 1968 - REVISED JANUARY 1996 • Inputs Are TTL-Voltage Compatible • Package Options Include Plastic Small-Outllne D , Shrink Small-Outllne (DB), Thin Shrink Small-Outllne (PW),

body marking TPS

Contextual Info: TPS3705-30, TPS3705-33, TPS3705-50 TPS3707-25, TPS3707-30, TPS3707-33, TPS3707-50 PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS184B - N O VEM BE R 1998 - R EVISED JA N U A R Y 1999 TPS3705 . . . D PACKAGE TOP VIEW (features Power-On Reset Generator with Fixed

74ACT11086

Contextual Info: 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES T 10185— D3390, N O VEM BER 1969 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout TOP VIEW

SN54HCT02

Abstract: SN74HCT02
Contextual Info: SN54HCT02, SN74HCT02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS065A - N O VEM B ER 1988 - R EVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outline D and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and

si1220

Abstract: differential line driver and receiver pair SN65LVDS050 SN65LVDS051 SN65LVDS179 SN65LVDS180 SLLS301C-APRIL
Contextual Info: SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLLS301C - AP R IL 1998 - REVISED N O VEM BER 1998 • • • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Signaling Rates up to 400 Mbps

16T MARKING

Abstract: ANA 618 TL16C550 74LS245 TL16C450 TL16C452 TL16C550B MCR 2225 lpc 2238
Contextual Info: TL16C552AI DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS 189A - N O VEM BER 1994 - REVISED M ARCH 1996 • Programmable Serial Interface Characteristics for Each Channel: - 5-, 6-, 7-, or 8-Bit Characters - Even, Odd, or No Parity Bit Generation

Contextual Info: T1SP3290 DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS Copyright 1997, P ow e rIn o w rtom Limned, UK NO VEM BER 1886 - REVISED SEPTEM B ER 1987 TELECOMMUNICATION SYSTEM SECONDARY PROTECTION • lon-lm plarrted Brssfcdown Region P recise end Stable Voltage

ahct16245

Abstract: SN54AHCT16245 SN74AHCT16245 MH723
Contextual Info: SN54AHCT16245, SN74AHCT16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCLS335A - M A R C H 1996 - R EVISED N O VEM B ER 1996 Members of the Texas Instruments Widebus Family SN54AHCT16245 . . . WD PACKAGE SN74AHCT16245 . . . DGG OR DL PACKAGE TOP VIEW

54ACT11827

Abstract: 74ACT11827
Contextual Info: 54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS I D3373, NO VEM BER 1989 - REVISED A P R IL 1993 _ • I I I | * Inputs Are TTL-Voltage Compatible * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

SCR Gate Drive

Abstract: tl7770
Contextual Info: TL7770-5, TL7770-12, TL7770-15 DUAL POWER-SUPPLY SUPERVISORS _D3035, OCTO BER 1987-R E V IS E D NO VEM BER 1991 • D W ,J,O R N PACKAGE TOP VIEW Power-On Reset Generator Automatic Reset Generation After Voltage Drop 1 RESIN [ 1 16 ] V CC 15 ] 2RESIN

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _SCAS337B - FEBRU A RY 1993 - REV ISED NO VEM BER 1995 * Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vqc Distributes One Clock input to Twelve

SN74ALVCH16600

Contextual Info: SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS S C E S 030A - JULY 1995 - REVISED N O VEM BER 1996 Member of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process UBT™ (Universal Bus Transceiver)

SN74ALVCH16501

Abstract: X12V
Contextual Info: SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS S C E S 024A - JULY 1995 - REVISED N O VEM BER 1996 DGG OR DL PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family E P IC ™ (Enhanced-Performance Implanted CMOS) Submicron Process

Contextual Info: 74ACT11825 8-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS S C A S 154A - D3715, NO VEM BER 1990 - R EVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW PACKAGE TOP VIEW Multiple Output Enables Allow Multiuser Control of the Interface OËT[ 1Q [ 2Q [

SN65LVDS93

Abstract: interlace parity DS90CR285 SN65LVDS94 SN74FB2032 SN74FB203
Contextual Info: SN65LVDS93 N-LINK TRANSMITTER S LLS 302A - MAY 1998 - REVISED N O VEM BER 1998 28:4 Data Channel Compression at up to 1.82 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI DGG PACKAGE TOP VIEW V CC [ 1 #

SN75LVDS93

Abstract: SN75LVDS94 DS90CR286 SN65LVDS93 SN65LVDS94 SN65LVDS95 microwave transceiver 3.9 8 bit Parallel-Out Shift Register
Contextual Info: SN65LVDS94 N-LINK RECEIVER S LLS 298A - MAY 1998 - REVISED N O VEM BER 1998 • • • • 4:28 Data Channel Expansion at up to 1.820 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI DGG PACKAGE TOP VIEW

CDCR81

Abstract: MO-137
Contextual Info: CDCR81 DIRECT RAMBUS CLOCK GENERATOR S C A S 6 0 6 - N O VEM BER 1998 DBQ PACKAGE TOP VIEW 400-MHz Differential Clock Source for Direct Rambus Memory Systems for an 800-MHz Data Transfer Rate • Synchronizes the Clock Domains of the Rambus Channel With an External System

it4140

Contextual Info: SN74LVC16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS I SCAS31 SB - N O VEM BER 1993 - R EVISED JULY 1995 Member of the Texas Instruments Wldebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process DQQ OR DL PACKAGE (TOP VIEW)