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    VHDL CODE LINEAR BLOCK CODE Search Results

    VHDL CODE LINEAR BLOCK CODE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TC75S102F Toshiba Electronic Devices & Storage Corporation Operational Amplifier, 1.5V to 5.5V, I/O Rail to Rail, IDD=0.27μA, SOT-25 Visit Toshiba Electronic Devices & Storage Corporation
    TCR5RG28A Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 2.8 V, 500 mA, WCSP4F Visit Toshiba Electronic Devices & Storage Corporation
    TCR3DM18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 300 mA, DFN4 Visit Toshiba Electronic Devices & Storage Corporation
    TCR3DG18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 300 mA, WCSP4E Visit Toshiba Electronic Devices & Storage Corporation
    TCR2EF18 Toshiba Electronic Devices & Storage Corporation LDO Regulator, Fixed Output, 1.8 V, 200 mA, SOT-25 (SMV) Visit Toshiba Electronic Devices & Storage Corporation

    VHDL CODE LINEAR BLOCK CODE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    vhdl code for ofdm

    Abstract: vhdl code for ofdm transmitter OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation OFDM matlab program CODES VHDL PROGRAM for ofdm vhdl code for 8 point ifft in xilinx simulation for prbs generator in matlab vhdl code for block interleaver
    Text: MW_DVB-T/H_P DVB Terrestrial/Handheld Modulator Core February 5, 2008 Product Specification AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files


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    code iir filter in vhdl

    Abstract: digital IIR Filter VHDL code xilinx vhdl code for digital clock vhdl code for ofdm VHDL code for Real Time Clock VHDL PROGRAM for ofdm ofdm matlab simulation block dvb-t matlab simulation code vhdl code for dvb-t OFDM Matlab code
    Text: MW_DVB-T/H_FP DVB Terrestrial/Handheld Filter Core February 15, 2008 Product Specification AllianceCORE Facts Provided with Core Documentation User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files


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    vhdl code for ofdm

    Abstract: ofdm matlab simulation block prbs generator using vhdl vhdl code for 16 prbs generator vhdl code for pseudo random sequence generator vhdl code for block interleaver vhdl code for interleaver ofdm code in vhdl vhdl code for ofdm transmitter DVB-T modulator
    Text: MW_DVB-T/H DVB Terrestrial/Handheld Modulator Core February 5, 2008 Product Specification AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files


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    dvb-t matlab simulation code

    Abstract: vhdl code for dvb-t DVB-T modulator VHDL code for Real Time Clock xilinx vhdl code for digital clock vhdl code for dvb-t 2 vhdl code for ofdm vhdl code for ofdm transmitter OFDM Matlab code television signal modulator
    Text: MW_DVB-T/H_F DVB Terrestrial/Handheld Filter Core February 15, 2008 Product Specification AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files


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    dvbt transmitter

    Abstract: Xilinx asi vhdl coding for error correction and detection dvb-t transmitter DVB-T modulator vhdl code for dvb-t serial parallel transport stream vhdl code for spi audio file in vhdl code vhdl code for ofdm transmitter
    Text: MW_DVB-T/H_A ASI/SPI Interface Core March 18, 2008 Product Specification AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files Centro Direzionale Colleoni


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    simulation for prbs generator in matlab

    Abstract: block diagram prbs generator in matlab vhdl code for pseudo random sequence generator in vhdl code for 16 prbs generator vhdl code for pseudo random sequence generator prbs pattern generator using vhdl pulse shaping FILTER implementation xilinx vhdl code for 7 bit pseudo random sequence generator fifo vhdl xilinx rAised cosine FILTER
    Text: MW_ATSC ATSC Modulator Core February 5th , 2008 Product Specification AllianceCORE Facts Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files Centro Direzionale Colleoni


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    synchronous fifo design in verilog

    Abstract: asynchronous fifo vhdl xilinx vhdl code for asynchronous fifo xilinx asynchronous fifo fifo vhdl xilinx vhdl code for fifo vhdl code for a grey-code counter ram 512x8 8 bit ram using vhdl fifo vhdl
    Text: Application Note: Spartan-II FPGAs R XAPP175 v1.0 November 23, 1999 High Speed FIFOs In Spartan-II FPGAs Application Note Summary This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan -II FPGAs. Verilog and VHDL code is available for the design. The


    Original     		PDF XAPP175 512x8 XC2S15 synchronous fifo design in verilog asynchronous fifo vhdl xilinx vhdl code for asynchronous fifo xilinx asynchronous fifo fifo vhdl xilinx vhdl code for fifo vhdl code for a grey-code counter ram 512x8 8 bit ram using vhdl fifo vhdl

    vhdl code 16 bit LFSR

    Abstract: vhdl code 8 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR vhdl code 16 bit LFSR with VHDL simulation output verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR verilog code 5 bit LFSR pseudo random generator
    Text: Channel January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and


    Original     		PDF I-10148 vhdl code 16 bit LFSR vhdl code 8 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR vhdl code 16 bit LFSR with VHDL simulation output verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR verilog code 5 bit LFSR pseudo random generator

    vhdl code for branch metric unit

    Abstract: processor control unit vhdl code processor control unit vhdl code download vhdl coding for hamming code branch metric vhdl code 16 bit processor hamming decoder vhdl code 5 to 32 decoder using 3 to 8 decoder vhdl code Radix selection unit radix 2 verilog
    Text: VITERBI_DEC Viterbi Decoder January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and


    Original     		PDF I-10148 vhdl code for branch metric unit processor control unit vhdl code processor control unit vhdl code download vhdl coding for hamming code branch metric vhdl code 16 bit processor hamming decoder vhdl code 5 to 32 decoder using 3 to 8 decoder vhdl code Radix selection unit radix 2 verilog

    MC6845

    Abstract: address generator logic vhdl code vhdl code for character display scrolling C6845 vhdl code for light control
    Text: C6845 CRT Controller Megafunction General Description The C6845 Cathode Ray Tube Controller CRTC interfaces a microprocessor to a raster-scan CRT display. The C6845 is a synchronous, synthesizable VHDL megafunction, functionally equivalent to the Motorola


    Original     		PDF C6845 C6845 MC6845 address generator logic vhdl code vhdl code for character display scrolling vhdl code for light control

    rx data path interface in vhdl

    Abstract: vhdl code for 8-bit calculator CRC-16 CRC-32 STS-48 CC226 x431 fpga vhdl code for crc-32 CRC-16 and verilog vhdl code for scrambler descrambler
    Text: CoreEl 1.25 Gb/s GFP Framer CC224 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation CC224 Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral


    Original     		PDF CC224) CC224 apCC224 rx data path interface in vhdl vhdl code for 8-bit calculator CRC-16 CRC-32 STS-48 CC226 x431 fpga vhdl code for crc-32 CRC-16 and verilog vhdl code for scrambler descrambler

    CC226

    Abstract: simple powerful charge controller block diagram vhdl code for 8-bit calculator register based fifo xilinx crc verilog code 16 bit vhdl code for scrambler descrambler CRC-16 CRC-32 rx data path interface in vhdl vhdl code CRC32
    Text: CoreEl 2.5 Gb/s GFP Framer CC226 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral


    Original     		PDF CC226) CC226 simple powerful charge controller block diagram vhdl code for 8-bit calculator register based fifo xilinx crc verilog code 16 bit vhdl code for scrambler descrambler CRC-16 CRC-32 rx data path interface in vhdl vhdl code CRC32

    CRC-16 and verilog

    Abstract: vhdl code scrambler CRC-16 CRC-32 OTN SWITCH header G.7041 GFP XC2V500-5 CRC-16 and CRC-32 Ethernet
    Text: CoreEl 8-Bit Multichannel GFP Framer CC225 May 30, 2003 Product Specification AllianceCORE™ Facts Core Specifics See Table 1 Provided with Core Documentation CC225 Functional Specification Design File Formats EDIF netlist Constraints File .ucf Script Based Behavioral


    Original     		PDF CC225) CC225 apCC225 CRC-16 and verilog vhdl code scrambler CRC-16 CRC-32 OTN SWITCH header G.7041 GFP XC2V500-5 CRC-16 and CRC-32 Ethernet

    RTL 8186

    Abstract: vhdl code for block interleaver turbo encoder circuit, VHDL code Turbo Code LogiCORE IP License Terms RTL 8190 32 bit adder vhdl code matlab code for half adder xilinx TURBO decoder XC4VLX60 8085 vhdl
    Text: IEEE 802.16e CTC Decoder Core DS137 v2.3 July 11, 2006 Product Specification Features • Performs iterative soft decoding of the IEEE 802.16e Convolutional Turbo Code (CTC) encoded data as described in Section 8.4 of the IEEE Std 802.16-2004 specification and the corrigendum IEEE


    Original     		PDF DS137 16-2004/Cor1/D5 RTL 8186 vhdl code for block interleaver turbo encoder circuit, VHDL code Turbo Code LogiCORE IP License Terms RTL 8190 32 bit adder vhdl code matlab code for half adder xilinx TURBO decoder XC4VLX60 8085 vhdl

    Meritec 800 860-9014

    Abstract: LFS File Manager Software vhdl code for home automation ,vhdl code for implementation of eeprom intel Programmers Reference Manual pAL programming Guide Block Management Layer Programmer eeprom programmer schematic flash memory databook Flash Memory Product Selector Guide
    Text: 6.0 THE µBGA* PACKAGE TOOLS AND SOFTWARE SUPPORT 6.1 Tools and Software Support Overview Regardless of what stage you are at in the definition, design, prototyping, or production process of your product, Intel supplies the tools and software support that saves you time and


    Original     		PDF 24-hours Meritec 800 860-9014 LFS File Manager Software vhdl code for home automation ,vhdl code for implementation of eeprom intel Programmers Reference Manual pAL programming Guide Block Management Layer Programmer eeprom programmer schematic flash memory databook Flash Memory Product Selector Guide

    vhdl code scrambler

    Abstract: scrambling design of scrambler and descrambler verilog code for implementation of des error correction code in vhdl vhdl code Linear block code Scrambler vhdl code for pseudo random sequence generator crc 16 verilog vhdl code CRC 32
    Text: DSS Distributed Sample Scrambler January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and


    Original     		PDF I-10148 vhdl code scrambler scrambling design of scrambler and descrambler verilog code for implementation of des error correction code in vhdl vhdl code Linear block code Scrambler vhdl code for pseudo random sequence generator crc 16 verilog vhdl code CRC 32

    CoolRISC 816

    Abstract: verilog code voltage regulator vhdl project of 16 bit microprocessor using vhdl abstract for UART simulation using VHDL Jaquet vhdl code for digital to analog converter Jaquet speed block diagram UART using VHDL vhdl code for march c algorithm "Heat meter"
    Text: ESPRIT DESIGN CLUSTER Action Task 2.28 DIRECTORATE GENERAL III Industry RTD : Information Technologies Contract n° EP 25213 TARDIS MEthodology for LOw Power ASic design MELOPAS DESIGN STORY December 6th, 2000 This document may be published without any restrictions


    Original     		PDF DATE-2000 CoolRISC 816 verilog code voltage regulator vhdl project of 16 bit microprocessor using vhdl abstract for UART simulation using VHDL Jaquet vhdl code for digital to analog converter Jaquet speed block diagram UART using VHDL vhdl code for march c algorithm "Heat meter"

    vhdl code hamming

    Abstract: vhdl coding for hamming code vhdl code for pipelined matrix multiplication vhdl code for matrix multiplication vhdl code hamming ecc parity ECC SEC-DED Hamming code SRAM verilog code for matrix multiplication SECDED RTAX2000S vhdl code SECDED
    Text: Application Note AC273 Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs Applies to EDAC Core from Libero IDE v7.1 or Older Introduction Actel's newest designed-for-space Field Programmable Gate Array FPGA family, the RTAX-S, is a highperformance, high-density antifuse-based FPGA with embedded user static RAM (SRAM). Based on Actel's


    Original     		PDF AC273 l011011101101 vhdl code hamming vhdl coding for hamming code vhdl code for pipelined matrix multiplication vhdl code for matrix multiplication vhdl code hamming ecc parity ECC SEC-DED Hamming code SRAM verilog code for matrix multiplication SECDED RTAX2000S vhdl code SECDED

    Companding

    Abstract: G711 G711-CMP G711-EXP
    Text: SPEECH CODECS INVENTRA TM T H E I N T E L L I G E N T A P P R O A C H T O I N T E L L E C T U A L P R O P E R T Y G711 - CMP G.711 PCM COMPRESSING FUNCTION F E AT U R E S DELIVERABLES u Compresses 13/14 bit linear PCM to 8 bit logarithmic A or Mu-law PCM


    Original     		PDF PD-30504 003-FO Companding G711 G711-CMP G711-EXP

    vhdl code 32 bit risc code

    Abstract: 32 bit risc processor using vhdl vhdl code for 32bit data memory central security system vhdl code for memory card ST22 vhdl code for risc processor vhdl code for uart communication FIPS-140 ST22XJ64
    Text: ST22XJ64 SMARTCARD 32-BIT RISC MCU WITH 64 KBYTES EEPROM AND JAVACARD HARDWARE EXECUTION DATA BRIEFING ST22XJ64 FEATURES • 32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING – 1 to 128 bytes Erase or Program in 2 ms typical ■ HIGH PERFORMANCE MEMORY


    Original     		PDF ST22XJ64 32-BIT ST22XJ64 24-BIT 160c/PRZ 160d/PRZ vhdl code 32 bit risc code 32 bit risc processor using vhdl vhdl code for 32bit data memory central security system vhdl code for memory card ST22 vhdl code for risc processor vhdl code for uart communication FIPS-140

    XAPP029

    Abstract: adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator Insight Spartan-II demo board XAPP172 xilinx XC3000 SEU testing verilog hdl code for triple modular redundancy parallel to serial conversion vhdl IEEE paper
    Text: DataSource CD-ROM Q4-01 Xilinx Application Note Summaries XAPP004 Loadable Binary Counters The design strategies for loadable and non-loadable binary counters are significantly different. This application note discusses the differences, and describes the design of a loadable binary counter.


    Original     		PDF Q4-01 XAPP004 XAPP005 XC3000 Desi49 XC18V00, XC9500XL, XC9500XV, XAPP501 XC9500, XAPP029 adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA vhdl code for pn sequence generator Insight Spartan-II demo board XAPP172 xilinx XC3000 SEU testing verilog hdl code for triple modular redundancy parallel to serial conversion vhdl IEEE paper

    G711

    Abstract: G711-CMP G711-EXP u 711
    Text: SPEECH CODECS INVENTRA TM T H E I N T E L L I G E N T A P P R O A C H T O I N T E L L E C T U A L P R O P E R T Y G711 - EXP G.711 PCM EXPANDING FUNCTION F E AT U R E S DELIVERABLES u Expands 8 bit logarithmic A or Mu-law PCM to 13/14 bit linear PCM u Purely combinational logic implementation


    Original     		PDF G711-CMP) PD-30507 001-FO G711 G711-CMP G711-EXP u 711

    verilog code for DFT

    Abstract: OFDMA Matlab code 8 point fft code in vhdl verilog code for FFT vhdl cyclic prefix code fft dft MATLAB vhdl code for FFT 512-point vhdl code for lte turbo MIMO Matlab code vhdl for 8 point fft
    Text: Channel card series — 3GPP Long-Term Evolution Altera wireless solutions Simplify your 3GPP LTE channel card design cycle Design for volume, design with agility Altera’s 3GPP Long-Term Evolution LTE portfolio of wireless solutions enables you to design your


    Original     		PDF specifying1332 SS-01036-1 verilog code for DFT OFDMA Matlab code 8 point fft code in vhdl verilog code for FFT vhdl cyclic prefix code fft dft MATLAB vhdl code for FFT 512-point vhdl code for lte turbo MIMO Matlab code vhdl for 8 point fft

    fpga vhdl code for crc-32

    Abstract: crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16
    Text: CoreEl CC327 10Gb GFP Framer May 6, 2003 Product Specification AllianceCORE™ Facts Paxonet Communications, Inc. 4046 Clipper Court Fremont CA 94538, USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 E-mail: sales@paxonet.com URL: www.paxonet.com Features


    Original     		PDF CC327 OC-192 fpga vhdl code for crc-32 crc verilog code 16 bit verilog code for 10 gb ethernet verilog code for frame synchronization sonet testbench XC2VP20 vhdl code scrambler STM 64 FRAMER WITH OTN vhdl code stm-64 CRC-16