VQC 10 D Y3 Search Results

Contextual Info: g Military 54F02 MOTOROLA Quad 2-Input NOR Gate MPO ELECTRICALLY TESTED PER: MIL-M-38510/33301 lllllll LOGIC DIAGRAM Vqc Y4 B4 A4 Y3 B3 A3 AVAILABLE AS: 1) JAN: JM38510/33301BXA 2) SMD: N/A 3)883: 54F02/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: C

Contextual Info: g MOTOROLA M ilitary 54F11 Triple 3-Input AND Gate MP0 ELECTRICALLY TESTED PER: MIL-M-38510/34002 « ///// LOGIC DIAGRAM Vqc C1 Y1 C3 B3 A3 Y3 nri frri [TT] rrn H nn it i AVAILABLE AS: 1) JAN: JM38510/34002BXA 2) SMD: N/A 3 )8 8 3 : 54F11/BXAJC X = CASE OUTLINE AS FOLLOWS:

DM54S189AJ

Abstract: DM54S189J DM74S189 DM74S289 S189 DM74S189N DM54S189
Contextual Info: DM54S189/DM74S189/DM54S189A/DM7 4S189 A National Ju i Semiconductor DM54S189/DM74S189 64-Bit 16 x 4 TRI-STATE RAM DM54S189A/DM74S189A High Speed 64-Bit TRI-STATE RAM General Description available at the outputs when the read/write input is high and the chip-enable is low. When the chip-enable is high,

54LS132

Abstract: 1N3064 1-INPUT NAND SCHMITT TRIGGER 54LS132 MOTOROLA
Contextual Info: M Military 54LS132 M O TO RO LA Quad 2-Input Schmitt-TVigger Positive NAND Gate MPO ELE C TR IC A LLY TESTED PER: M IL-M -38510/31303 H U M The 54LS132 contains four 2-input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They

Contextual Info: NATIONAL SEMICOND -CLOGICJ IDE D | bSD1155 0DbSS71 3 | s 5E oi National Semiconductor 3 ä MM54HCT00/MM74HCT00 Quad 2 Input NAND Gate s General Description X o H o o The MM54HCT00/MM74HCT00 are NAND gates fabricated using advanced silicon-gate CMOS technology which pro­

398B

Abstract: J-131 DM54LS86J DM54LS86W DM74LS86 DM74LS86M DM74LS86N J14A M14A N14A
Contextual Info: S E M IC O N D U C T O R tm DM74LS86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which perform s the logic exclusive-O R function. Connection Diagram D ual-ln-Line Package Vcc | 14 B4 A4 13 Y4 12

ic 747 cn

Abstract: 74als747 LS747
Contextual Info: SN 54A LS746, SN 54A LS747, SN 74A LS746, SN 74A LS747 OCTAL BUFFERS AND LINE DRIVERS WITH INPUT PULL-UP RESISTORS AU G U S T 1 9 8 4 - • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers REVISED M A Y 1 9 8 6 S N 5 4 A L S 7 4 6 , S N 5 4 A L S 7 4 7 . . . J PACKAGE

VHC126

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad Bus Buffer MC74VHC126 w ith 3-S ta te Control Inputs The MC74VHC126 is a high speed CMOS quad bus buffer fabricated with silicon gate CM OS technology. It achieves noninverting high speed operation similar to equivalent Bipolar Schottky TTL while maintaining

54LS32

Contextual Info: g M ilitary 54LS32 MOTOROLA Quad 2-Input OR Gate MP0 ELECTRICALLY TESTED PER: MIL-M-38510/30501 LOGIC DIAGRAM Vqc ra B4 A4 Y4 r ii füi [Tn B3 A3 m in t Y3 Roí nn m AVAILABLE AS: 1) JAN: JM38510/30501BXA 2) SMD: N/A 3)883: 54LS32/BXAJC X = CASE OUTLINE AS FOLLOWS:

Contextual Info: MOTOROLA M ilita ry 54F 3 2 Quad 2-In p u t OR G ate MPO ELECTRICALLY TESTED PER: MIL-M-38510/33501 HUM LOGIC DIAGRAM VqC A4 B4 Y4 B3 A3 Y3 AVAILABLE AS: 1 JAN: JM38510/33501BXA 2) SMD: N/A 3) 883: 54F32/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CEROIP: C

Contextual Info: d t M ULTILEVEL PIPELINE REGISTERS IDT29FCT520A/B !D T 29FC T521A / b FEATURES: DESCRIPTION: • Equivalent to AMD’s Am29520/21 bipolar Multilevel Pipeline Registers in pinout/function, speeds and output drive over full temperature and voltage supply extremes

Contextual Info: HIGH-PERFORMANCE CMOS BUFFERS ¡n í^ r r í^ o IDT54/74FCT828A/B FEATURES: DESCRIPTION: • Faster than AMD’s Am29827-28 series The IDT54/74FCT800 Series is built using advanced CEMOS , a dual metal CMOS technology. The IDT54/74FCT827A/B and IDT54/74FCT828A/B 10-bit bus

Contextual Info: lljljfiv Integrated DeviœTèchnology. Inc PRELIMINARY IDT 7320 IDT 7321 16-BIT CMOS MULTILEVEL PIPELINE REGISTERS FEATURES: DESCRIPTION • IDT7320: E ig h t 16-bit h ig h -sp e e d p ip e lin e registers • IDT7321: S even 16-bit h ig h -s p e e d p ip e lin e re giste rs p lu s a

Contextual Info: MOTOROLA Military 54LS04 Hex-Input Inverter Gate ELECTRICALLY TESTED PER: MIL-M-38510/30003 M Vqc A6 Y6 A5 Y5 A4 P 0 lllllll LOGIC DIAGRAM Y4 AVAILABLE AS: 1 JAN: JM38510/30003BXA 2) SMD: N/A 3)883: 54LS04/BXAJC X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: C

Contextual Info: MOTOROLA M ilita ry 54L S 2 6 6 Quad 2-In pu t Exclusive NOR G ate ELECTRICALLY TESTED PER: MIL-M-38510/30303 MPO unw LOGIC DIAGRAM Vcc B4 A4 Y3 B3 A3 AVAILABLE AS: ? A1 Y4 1 JAN: JM38510/30303BXA 2) SMD: N/A 3)883: 54LS266/BXAJC <51 B1 Y1 Y2 A2 B2 X = CASE OUTLINE AS FOLLOWS:

54ALS08

Abstract: Y411
Contextual Info: MOTOROLA Military 54ALS08 Quad 2-Input Positive AND Gate ELECTRICALLY TESTED PER: MPG54ALS08 AVAILABLE A S: L O G IC D IA G R A M B4 Vqc fi^l A4 Y4 B3 Rai Rii F I A3 1 JAN : N/A 2) SM D: N/A 3) 883C: 54ALS08/BXAJC Y3 nói ITI ITI X = C A S E OUTLINE A S FO LLOW S:

Contextual Info: M MOTOROLA M ilita ry 5 4 F 1 3 2 Quad 2-In p u t NAND S c h m itt TVigger ELECTRICALLY TESTED PER: MPG54F132 H P O m B4 A4 Y4 B3 i AVAILABLE AS: LOGIC DIAGRAM VCC in A3 1) JAN: N/A 2) SMD: N/A 3)883: 54F132/BXAJC Y3 X = CASE OUTLINE AS FOLLOWS: PACKAGE: CERDIP: C

Contextual Info: CO æ jg i National Æiâ Semiconductor DM54S86/DM74S86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which performs the logic Exclusive-OR function. Connection Diagram Dual-In-Line Package V cc | 14

Contextual Info: g Military 54LS32 MOTOROLA Quad 2-Input OR Gate MP0 mini ELECTRICALLY TESTED PER: MIL-M-38510/30501 LOGIC DIAGRAM VCC ra B4 A4 [iii n il Y4 im B3 Hoi A3 in Y3 nn AVAILABLE AS: 1) JAN: JM38510/30501BXA 2) SMD: N/A 3)883: 54LS32/BXAJC X = CASE OUTLINE AS FOLLOWS:

Contextual Info: MM54HCT139/MM74HCT139 National Semiconductor PRELIMINARY microCMOS M M 54H C T 139/M M 74H C T 13 9 D u al 2-TO -4 L in e D e c o d e r General Description The MM54HCT139/MM74HCT139 is a high speed sllicongate CMOS decoder that is well suited to memory address

SN54ALS138

Abstract: SN54AS138 SN74ALS138 SN74AS138
Contextual Info: SN 54A LS138, S N 54A S 138, SN 74A LS138, SN 74A S138 3-LINE TO 8 LINE DECODERS/DEMULTIPLEXERS D 2 6 6 1 , A P R IL 1 9 8 2 - R E V IS E D M A Y 1 9 8 6 S N 5 4 A L S 1 3 8 , S N 5 4 A S 1 3 8 . . . J PACKAGE S N 7 4 A L S 1 3 8 , S N 7 4 A S 1 3 8 . . . D OR N PACKAGE

74ABT125

Abstract: 74ABT125D 74ABT125N 74ABT125PW
Contextual Info: Philips Sem iconductors Product specification Quad buffer 3-State 74ABT125 FEATURES DESCRIPTION • Q uad bus interface The 74ABT125 high-perform ance BiCMOS device com bines low static and dynam ic power dissipation with high speed and high output drive.

74ALS541A

Contextual Info: TYPES SN54ALS540, SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3 STATE OUTPUTS D2661. APRIL 1982-REVISED DECEMBER 1983 3-S tate Outputs Drive Bus Lines or Buffer Mem ory Address Registers S N 5 4 A L S 5 4 0 , S N 5 4 A L S 5 4 1 . . . J PACKAGE

AHC540

Abstract: SN54AHC540 SN74AHC540
Contextual Info: SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260C - DECEMBER 1995 - REVISED JUNE 1996 Operating Range 2-V to 5.5-V Vqc SN54AHC 540 . . . J OR W PACKAGE SN74AHC 540 . . . DB, DW, N, OR PW PACKAGE TO P VIEW EPIC (Enhanced-Performance Implanted