XC95288 Search Results

Contextual Info: flXIUNX XC95288XL High Performance CPLD September 28,1998 Version 1.0 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depend­ ing on the system frequency, design application and output

XC95288

Contextual Info: flXIUNX XC95288 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fcN T 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

XC95288XL pinout

Abstract: XC95288XL XC95288XL-7PQ208I XC95288XL-7TQ144I XC95288XL-10PQ208I XC95288XL-10TQ144I marking G18 XC95288XL-10-PQ208 XC95288XL-6FG256C XAPP114
Contextual Info: XC95288XL High Performance CPLD DS055 v1.7 August 21, 2003 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)

XC95288XL10TQG144I pinout

Abstract: XC95288XL PQG208 XC95288XL pinout XC95288XL-10TQG144C fgg256 XC95288XL XC95288XL-7CS280C XC95288XL-10FGG256I XC95288XL-7TQ144I pqg208
Contextual Info: XC95288XL High Performance CPLD R DS055 v2.1 April 3, 2007 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins

XC95216-20PQG160I

Abstract: XC95216-15PQ160I 471 E25 XC95216 Family XC95216-10PQ160C XC95216-10PQ160I XC95216-15PQG160C XC95216-15PQG160I XC95216-10PQG160I XC9500
Contextual Info: XC95216 In-System Programmable CPLD R 5 Note: The 352-pin BGA packages are being discontinued for XC95216 devices. You cannot order these packages after May 14, 2008. Xilinx recommends replacing XC95216 in 352-pin BGA packages with XC95288 devices in 352-pin BGA packages in all designs as soon as possible. Recommended replacements are pin compatible, but

TQ144

Abstract: XAPP361 XC9500XV XC95288XV XC95288XV-10 XC95288XV-7
Contextual Info: u XC95288XV High-Performance CPLD R DS050 v2.5 August 21, 2003 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)

XC95288

Abstract: BG352 HQ208 XC9500 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.1 August 21, 2003 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

471 E25

Abstract: xc95288 XC95288-15HQ208I AD9318 A23 780-4 BG352 HQ208 XC9500 h3144 n439
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.3 April 3, 2006 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC95288

Contextual Info: flX IU N X XC95288 In-System Programmable CPLD June 1, 1996 Version 1.0 Advance Product Specification Features Description • • The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of sixteen

F25-F26

Contextual Info: flXILINX XC95288 In-System Programmable CPLD N o vem b er 12, 1997 V ersion 2.0 Preliminary Product Specification Features MCHp (1.7) + MC lp (0.9) + MC (0.006 mA/MHz) f • 15 ns pin-to-pin logic delays on all pins • fcNT 95 MHz • 288 macrocells with 6,400 usable gates

Contextual Info: Product Obsolete/Under Obsolescence u XC95288XV High-Performance CPLD R DS050 v3.0 June 25, 2007 5 Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC95288XV devices with equivalent XC95288XL

XC95288

Abstract: Marking af1 AF24 marking
Contextual Info: XC95288 In-System Programmable CPLD R DS069 v4.2 April 15, 2005 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 166 user I/O pins 5V in-system programmable

XC95288

Abstract: HQ208
Contextual Info:  XC95288 In-System Programmable CPLD June 1, 1996 Version 1.0 Advance Product Specification Features Description • • • • • The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of sixteen

v19 423

Abstract: V19 312 TQ144 XC9500XL XC95288 XC95288XL w17 88
Contextual Info: 1 XC95288XL High Performance CPLD R June 7, 1999 Version 1.2 5* Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output

XC95288-15HQ208I

Abstract: XC95288
Contextual Info: Product Obsolete/Under Obsolescence XC95288 In-System Programmable CPLD R DS069 v5.0 May 17, 2013 5 Product Specification Features Description • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates

A23 780-4

Abstract: 471 E25 BG352 HQ208 XC9500 XC95288
Contextual Info: XC95288 In-System Programmable CPLD  November 12, 1997 Version 2.0 3* Preliminary Product Specification Features MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f • • • • • Where: • • • • • • • • • • • MCHP = Macrocells in high-performance mode

Contextual Info: tlXIUNX* XC95288 In-System Programmable CPLD J a n u a ry , 1 9 9 7 V e rs io n 1.0 Advanced Product Specification Features Description • 10 ns pin-to-pin logic delays on all pins • ^CNT to 111 MHz • • • 288 m acrocells with 6,400 usable gates

Contextual Info: XC95288XV High-Performance CPLD R DS050 v2.0 January 29, 2001 5 Advance Product Specification Features Power Estimation • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

Contextual Info: u XC95288XV High-Performance CPLD R DS050 v2.6 April 15, 2005 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)

XC95288

Abstract: BG352 HQ208 XC9500 X5906 X7131 HQ208I
Contextual Info: 1 XC95288 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

XC95288

Abstract: BG352 HQ208 XC9500
Contextual Info:  XC95288 In-System Programmable CPLD January, 1997 Version 1.0 Advanced Product Specification Features Description • 10 ns pin-to-pin logic delays on all pins • fCNT to 111 MHz • 288 macrocells with 6,400 usable gates • Up to 192 user I/O pins

TQ144

Abstract: XC9500XV XC95288XV XC95288XV-10 XC95288XV-5 XC95288XV-7 csp192 T9423 w7510
Contextual Info: XC95288XV High-Performance CPLD R DS050 v2.2 August 27, 2001 5 Advance Product Specification Features Power Estimation • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell

780 AC

Contextual Info: £ XILINX XC95288XL High Performance CPLD February 5, 1999 Version 1.1 Advance Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depend­ ing on the system frequency, design application and output

T9423

Abstract: TQ144 XC9500XL XC95288 XC95288XL W-7510 w7510 k1739
Contextual Info: XC95288XL High Performance CPLD DS055 v1.4 March 19, 2001 5 Features • • • • • • • • • • • 6 ns pin-to-pin logic delays System frequency up to 208 MHz 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins)