XC9536 44 PIN VQFP Search Results

XC9536

Abstract: XC9536-6 XC9536-7 XC9500 XC9536-10 XC9536-15 XC9536-5 xc9536 44 pin vqfp
Contextual Info: 9 1 XC9536 In-System Programmable CPLD  December 4, 1998 Version 5.0 1 1* Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins

Contextual Info: XC9536 In-System Programmable CPLD K X I L I N X June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fQisiy to 125 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins

Contextual Info: flX IU N X XC9536 In-System Programmable CPLD October 29, 1997 Version 2.0 Product Specification Features Power Management 5 ns pin-to-pin logic delays on all pins • • • • • • • • • • • • • fcNT to MHz 36 macrocells with 800 usable gates

XC9536-10PC44C

Contextual Info: XC9536 In-System Programmable CPLD R DS064 v6.0 June 18, 2003 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable

9536

Abstract: XC9500 XC9536 XC9536-10 XC9536-15 XC9536-5 XC9536-6 XC9536-7
Contextual Info: 9 1 XC9536 In-System Programmable CPLD  December 4, 1998 Version 5.0 1 1* Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins

XC9536

Abstract: xc9536 44 pin PC44 XC9536-10 XC9536-15 XC9536-5 XC9536-7 36V18 X5952
Contextual Info:  XC9536 In-System Programmable CPLD June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power

Contextual Info: flXIU N X XC9536 In-System Programmable CPLD December 4, 1998 Version 5.0 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • fcN T • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP)

XC9536-7

Abstract: XC9500 XC9536 XC9536-10 XC9536-15 XC9536-5
Contextual Info:  XC9536 In-System Programmable CPLD March, 1997 Version 1.1 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • fCNT to 100 MHz • 36 macrocells with 800 usable gates • Up to 34 user I/O pins • 5 V in-system programmable (ISP)

Contextual Info: HXILINX XC9536 In-System Programmable CPLD January, 1997 Version 1.0 Preliminary Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • • • • fcNT ^ MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins

Contextual Info: HXILINX XC9536 In-System Programmable CPLD November 10, 1997 Version 2.0 Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by config­ uring macrocells to standard or low-power modes of opera­

Contextual Info: £ XILINX XC9536 In-System Programmable CPLD June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fcNT "^25 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins

GTS FC-618A

Contextual Info: flX IU N X XC9536 In-System Programmable CPL June 3, 1998 Version 3.0 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • • • • fcNT to MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP)

XC9500

Abstract: XC9536 XC9536-10 XC9536-15 XC9536-5 XC9536-6 XC9536-7
Contextual Info: 9 XC9536 In-System Programmable CPLD  June 3, 1998 Version 3.0 3* Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power

xc9536 44 pin vqfp

Contextual Info: £ XILINX XC9536 In-System Programmable CPLD June 3 ,1 9 9 8 Version 3.0 Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC9536 by config­ uring macrocells to standard or low-power modes of opera­

xc9536

Contextual Info: KXILINX XC9536 In-System Programmable CPLD June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • 5 ns pin-to-pin logic delays on all pins fQfsjj to 125 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins

XAPP078

Abstract: xilinx xc9536 Schematic Abel code for johnson counter application johnson counter LM2940 LM2940CT-5 xilinx vhdl code for 555 timer TLC555 XC9500 XC9536
Contextual Info:  XAPP078 April, 1997 Version 1.0 XC9536 ISP Demo Board Application Note Summary The demo board described in this application note is a tool for demonstrating the In-System Programming (ISP) capabilities of the XC9500 CPLD family. Xilinx Family XC9500

xilinx xc9536 Schematic

Abstract: Xilinx jtag cable pcb Schematic Abel code for johnson counter xilinx vhdl code for 555 timer XC9536 vhdl code for 555 XAPP XC9536 PIN CONNECTION code voltage regulator vhdl LM2940CT-5
Contextual Info:  XAPP 078 March, 1997 Version 1.0 XC9536 ISP Demo Board Application Note Summary The demo board described in this application note is a tool for demonstrating the In-System Programming (ISP) capabilities of the XC9500 CPLD family. Xilinx Family XC9500

Contextual Info: flX IU N X XC9536 In-System Programmable CPLD November 10, 1997 Version 2.0 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • • • • fcNT to MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins

XC9536

Abstract: XC9536-10PC44C XC9500 XC9536-10 XC9536-15PC44C XC9536-5 XC9536-6 XC9536-7 xc9536 44 pin vqfp
Contextual Info: Datum 980916 PRODUKTINFORMATION HÄMTFAX 08-580 941 14 FAX ON DEMAND +46 8 580 941 14 INTERNET http://www.elfa.se TEKNISK INFORMATION 020-75 80 20 ORDERTEL 020-75 80 00 ORDERFAX 020-75 80 10 TECHNICAL INFORMATION +46 8 580 941 15 ORDERPHONE +46 8 580 941 01 ORDERFAX +46 8 580 941 11

XC9536

Abstract: XC9500 XC9536-10 XC9536-15 XC9536-5 XC9536-6 XC9536-7 95xxx xc9536 44 pin vqfp XC9536-10PC44
Contextual Info: XC9536 In-System Programmable CPLD R DS064 v6.1 August 21, 2003 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable

xc9536

Abstract: xc9536-7vq44 95xxx XC9536-7VQ44I xc9536-15vq44i XC9536-15VQ44C
Contextual Info: XC9536 In-System Programmable CPLD R DS064 v6.2 April 15, 2005 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable

Contextual Info: HXILINX XC9536 In-System Programmable CPLD Novem ber 2, 1998 Version 4.0 Product Specification Features Power Management • 5 ns pin-to-pin logic delays on all pins • ^CNT to 100 MHz • • • 36 m acrocells with 800 usable gates Up to 34 user I/O pins

xc9536

Abstract: xc9536 vqg44 XC9536-15VQG44I XC9536-5PCG44C XC9536-15PCG44C XC9536-15VQG44C XC9536-7PCG44I XC9536-10VQ44C XC9536-10VQG44C xc9536-7pc44c
Contextual Info: XC9536 In-System Programmable CPLD R DS064 v6.3 April 3, 2006 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable

xc9572-44 pin

Abstract: xc9536 44 pin vqfp XC9536 36V18 TQ100 VQ44 XC9500 XC9536-15VQ44Q XC9572 XC9572-15TQ100Q
Contextual Info: k XC9500 In-System Programmable CPLD Automotive IQ Family R DS120-1 v1.2 October 18, 2004 Features • System frequency up to 55 MHz • Guaranteed to meet full electrical specifications over TA = –40 to +125°C • 5V in-system programmable - Endurance of 10,000 program/erase cycles