Y1 DIODE Search Results

Contextual Info: Preliminary Specification V23870-A2121-Y 1X200 155 Mb/s, 1310 nm Tx / 1310 nm Rx Bi-Directional SFF Transceiver Ordering Information Input Output Signal Detect AC AC PECL DC DC PECL 1 2 Voltage 3.3V 3.3V Part Number V23870-A2111-Y1 100 V23870-A2111-Y1 200

Contextual Info: Internally Trimmed Precision IC Multiplier AD534 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS +VS –VS TRANSFER FUNCTION X1 V-TO-1 X2 Y1 TRANSLINEAR MULTIPLIER ELEMENT VOUT = A X1 – X2 (Y1 – Y2) – (Z1 – Z2) SF V-TO-1 Y2 Z1 High quality analog signal processing

CDCP1803

Abstract: CDCP1803RTHR JESD51-7 SLUA271
Contextual Info: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14

Contextual Info: CDCP1803 www.ti.com SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER Check for Samples: CDCP1803 FEATURES 1 S1 VDD0 Y0 Y0 VDD0 24 23 22 21 20 19 18 VDDPECL 2 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1

Contextual Info: CDCM1804 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER SCAS697 – JULY 2003 D Distributes One Differential Clock Input to VSS VDD0 Y0 Y0 VDD0 S1 24 23 22 21 20 19 15 Y1 VDDPECL 5 14 VDD1 VBB 6 13 VDD3 12 4 Y3 Y1 IN VDD2 IN 11

CDCP1803

Abstract: CDCP1803RTHR JESD51-7 SLUA271
Contextual Info: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14

Contextual Info: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14

Contextual Info: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727A − NOVEMBER 2003 − REVISED DECEMBER 2003 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14

CDCP1803

Abstract: JESD51-7 SLUA271
Contextual Info: CDCP1803 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004 D Distributes One Differential Clock Input to S2 Vdd0 /Y0 Y0 Vdd0 S1 24 23 22 21 20 19 18 S0 VddPECL 2 17 Vdd1 IN 3 16 Y1 IN 4 15 Y1 VddPECL 5 14

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

CDCM1804

Abstract: G003
Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

ad534 application

Abstract: AD734 similar of AD534 R31MA1 AD734BNZ AD534 AD734AQ AD734BQ RMS-to-DC Converter DC to 500 MHz RMS-to-DC Converter
Contextual Info: 10 MHz, Four-Quadrant Multiplier/Divider AD734 FEATURES FUNCTIONAL BLOCK DIAGRAM AD734 X1 X2 X = X1 – X2 XIF HIGH ACCURACY TRANSLINEAR CORE DD U0 DENOMINATOR CONTROL U1 U2 Y1 Y2 U XZ U XY ÷ U – Z + WIF W – ∞ AO ER RU YIF Y = Y1 – Y 2 Z = Z1 – Z2

CDCM1804

Abstract: G003
Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

Contextual Info: 10 MHz, Four-Quadrant Multiplier/Divider AD734 FUNCTIONAL BLOCK DIAGRAM FEATURES AD734 X1 X = X1 – X2 XIF X2 HIGH ACCURACY TRANSLINEAR CORE DD DENOMINATOR CONTROL U U0 U1 XZ U XY ÷ U – Z + WIF W – ∞ AO ER RU U2 Y1 YIF Y = Y1 – Y 2 Z = Z1 – Z2

74LS137

Abstract: 16y0y1 SN54LSXXXJ SN74LSXXXD SN74LSXXXN Y4 DIODE TTL 74ls137 diode high voltage Y5
Contextual Info: SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC 16 Y0 Y1 Y2 Y3 Y4 Y5 Y6 15 14 13 12 11 10 9 Y0 Y1 Y2 Y3 Y4 Y5 C GL G2 G1 Y6 Y7 A B

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

CDCM1804

Abstract: G003
Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

Contextual Info: CDCM1804 www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 1 VSS(1) 7 8 9 13 10 11 12 Thermal pad must be connected to VSS.

74LS137

Abstract: SN54LSXXXJ SN74LSXXXD SN74LSXXXN M 5229 751B-03
Contextual Info: SN54/74LS137 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES 3-LINE TO 8-LINE DECODERS/ DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY DATA OUTPUTS VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 16 15 14 13 12 11 10 9 Y0 Y1 Y2 Y3 Y4 Y5 C GL G2 G1 Y6 Y7 A B