Y1 XTAL 125MHZ Search Results

ad9850 Application

Abstract: c36crpx pn sequence generator Centronics connector current rating ad9850 am modulation AD9850/FSPCB SQUARE WAVE TO SINE WAVE schematic diagram 100hz SQUARE WAVE TO SINE WAVE schematic diagram Frequency Generator 1MHz Numerically Controlled Oscillator
Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC & High Speed Comparator DAC SFDR > 50 dB @ 40 MHz AOUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability +3.3 V or +5 V Single Supply Operation

Contextual Info: PI6LC4820 HiFlexTM Ethernet Network Clock Generator Features Description ÎÎ 3.3V supply voltage he PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate

XTAL 4P 20MHz

Abstract: GC2500076 PI6LC4820 qa1 smd PI6LC4820Z Saronix xtal Oscillator 49S SMD
Contextual Info: PI6LC4820 HiFlexTM Ethernet Network Clock Generator Features Description ÎÎ3.3V supply voltage The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate

Contextual Info: PI6LC4820 HiFlexTM Ethernet Network Clock Generator Features Description ÎÎ3.3V supply voltage The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate

Contextual Info: PI6LC4820 HiFlexTM Ethernet Network Clock Generator Features Description ÎÎ3.3V supply voltage The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate

Contextual Info: PI6LC4820 HiFlexTM Ethernet Network Clock Generator Features Description ÎÎ3.3V supply voltage The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate

Contextual Info: PI6LC4820 HiFlexTM Ethernet Network Clock Generator Features Description ÎÎ3.3V supply voltage The PI6LC4820 is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25Mhz crystal input, while the PLL loop is used to generate

AD9850

Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz A OUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 V or 5 V Single-Supply Operation

ad9850 Application

Abstract: AD9850
Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz A OUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 V or 5 V Single Supply Operation

ad9850 Application

Abstract: AD9850 CAPACITOR TANTALUM 2.2k 100V 100hz SQUARE WAVE TO SINE WAVE schematic diagram c36crpx AD9850BRSZ ad9850 am modulation panel mount banana jack ups PURE SINE WAVE schematic diagram AD9850BRS
Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz A OUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 V or 5 V Single-Supply Operation

AD9850

Abstract: ad9850 Application AD9850BRSZ-REEL AD9850BRS AD9850BRS-REEL AD9850BRSZ 9850REV2
Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz A OUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability 3.3 V or 5 V Single-Supply Operation

c36crpx

Abstract: ad9850 Application 9850REV2 AD9850 AD9850/FSPCB ad9850 modulation AD9850-SPECIFICATIONS 8bit pn sequence generator AD9059 AD9850BRS
Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz A OUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability +3.3 V or +5 V Single Supply Operation

ad9850 Application

Abstract: AD9850 AD9059 AD9850BRS function generator circuit schematic diagram full ad9850 modulation 74HCT574 c36crpx
Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC & High Speed Comparator DAC SFDR > 50 dB @ 40 MHz AOUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability +3.3 V or +5 V Single Supply Operation

ad9850 Application

Abstract: c36crpx AD9850 9850REV2 ad9850 am modulation AD9850/FSPCB ups PURE SINE WAVE schematic diagram AD9059 AD9850BRS 2526n
Contextual Info: a FEATURES 125 MHz Clock Rate On-Chip High Performance DAC and High Speed Comparator DAC SFDR > 50 dB @ 40 MHz AOUT 32-Bit Frequency Tuning Word Simplified Control Interface: Parallel Byte or Serial Loading Format Phase Modulation Capability +3.3 V or +5 V Single Supply Operation

Contextual Info: CDCE62002 www.ti.com SCAS882B – JUNE 2009 – REVISED FEBRUARY 2010 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs Check for Samples: CDCE62002 FEATURES 1 • • • • • • • • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter

Contextual Info: CDCE62002 www.ti.com SCAS882B – JUNE 2009 – REVISED FEBRUARY 2010 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs Check for Samples: CDCE62002 FEATURES 1 • • • • • • • • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter

S-PQFP-N32

Abstract: CDCE62002 UXP 600 G003 QFN-32 BIT29 texas instruments package designator
Contextual Info: CDCE62002 www.ti.com. SCAS882A – JUNE 2009 – REVISED JULY 2009 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002

Abstract: UXP 600 G003 QFN-32 S-PQFP-N32
Contextual Info: CDCE62002 www.ti.com. SCAS882A – JUNE 2009 – REVISED JULY 2009 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

VCO circuit diagram

Abstract: CDCE62002 G003 QFN-32 S-PQFP-N32 CORE23
Contextual Info: CDCE62002 SCAS882C – JUNE 2009 – REVISED MARCH 2011 www.ti.com Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs Check for Samples: CDCE62002 FEATURES 1 • • • • • • • • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter

Contextual Info: CDCE62002 SCAS882D – JUNE 2009 – REVISED FEBRUARY 2012 www.ti.com Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs Check for Samples: CDCE62002 FEATURES 1 • • • • • • • • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter

Contextual Info: CDCE62002 SCAS882D – JUNE 2009 – REVISED FEBRUARY 2012 www.ti.com Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs Check for Samples: CDCE62002 FEATURES 1 • • • • • • • • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter

SCAS882D

Abstract: CDCE62002
Contextual Info: CDCE62002 SCAS882D – JUNE 2009 – REVISED FEBRUARY 2012 www.ti.com Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs Check for Samples: CDCE62002 FEATURES 1 • • • • • • • • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter

CDCE62002

Abstract: CDCE62005 G003 QFN-32 S-PQFP-N32
Contextual Info: CDCE62002 www.ti.com. SCAS882 – JUNE 2009 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002

Abstract: CDCE62005 G003 QFN-32 S-PQFP-N32 12500MHz automatic ac 2kv voltage regulator circuit diagram
Contextual Info: CDCE62002 www.ti.com. SCAS882 – JUNE 2009 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs