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W160-7K

Abstract: lcd with led backlight 40 pin connector pinout W160-7KHC T6963C W160-7KHLW lcd t6963 screen led 16*128 CFL-160-7 EA KF100-20 W160-7
Contextual Info: EA W160-7K 4.2005 LCD- GRAPHIC MODULE BLUE / WHITE 160x128 DOTS WITH CONTROLLER T6963C Outline dimensions: 140x102x16mm FEATURES * * * * * * * * * HIGH CONTRAST STN TECHNOLOGY, NEGATIVE BLUE, BOTTOM VIEW CONTROLLER T6963C BUILT-IN 8-BIT BUS INTERFACE ASCII CHARACTER SET BUILT-IN

act175

Abstract: 54ACT175DMQB
Contextual Info: 54AC175 • 54ACT175 Quad D Flip-Flop General Description The ’AC/’ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both

Contextual Info: 54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop Simultaneous LOW on CD and SD makes both Q and Q General Description The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

JM54ACT151S2A-R

Abstract: 54ACT151FMQB
Contextual Info: 54AC151 • 54ACT151 8-Input Multiplexer General Description Features The ’AC/’ACT151 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one line of data from up to eight sources. The ’AC/’ACT151 can be used

ds26ls31m

Abstract: 5962-7802301Q2A
Contextual Info: DS26LS31C/DS26LS31M Quad High Speed Differential Line Driver General Description Features The DS26LS31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26LS31 meets all the requirements of EIA Standard RS-422 and Federal Standard 1020. It is designed to provide

Contextual Info: 54ACT399 Quad 2-Port Register General Description Features The ’AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flop on the rising

5962-8995001MFA

Abstract: 5962-8995001B2A smd SD1
Contextual Info: 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’ACT112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly

5962-7802005MEA

Abstract: M5962 5962-7802005M2A
Contextual Info: DS26F32M Quad Differential Line Receivers General Description Features The DS26F32 is a quad differential line receiver designed to meet the requirements of EIA Standards RS-422 and RS-423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission.

Contextual Info: 54AC257 • 54ACT257 Quad 2-Input Multiplexer with TRI-STATE Outputs General Description Features The ’AC/’ACT257 is a quad 2-input multiplexer with TRI-STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four

26c32at

Abstract: 26c32a 26C32AM 26c32
Contextual Info: DS26C32AT/DS26C32AM Quad Differential Line Receiver General Description Features The DS26C32A is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS.

Contextual Info: 54AC158 • 54ACT158 Quad 2-Input Multiplexer General Description The ’AC/’ACT158 is a high-speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the inverted form. The ’AC/’ACT158 can

Contextual Info: 54AC251 • 54ACT251 8-Input Multiplexer with TRI-STATE Output General Description The ’AC/’ACT251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal

burndy Y35 Hypress owner manual

Abstract: burndy Y39 Hypress owner manual Burndy Y35 hypress burndy Y35 burndy Y750 UL-467 Penetrox A Electric Joint Compound Y750 REVOLVER HYPRESS GBM STEP MOTOR burndy Y750HS user manual
Contextual Info: GC-08 www.burndy.com CALL 1-800-346-4175 FOR YOUR LOCAL SALES REPRESENTATIVE BURNDY PRODUCTS BURNDY PRODUCTS Grounding Catalog Experience. Technology. Answers. Customer Service Dept. 7 Aviation Park Drive Londonderry, NH 03053 1-800-346-4175 Canada 1-800-361-6975 Quebec

54FCT138DMQB

Contextual Info: 54FCT138 1-of-8 Decoder/Demultiplexer General Description Features The FCT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three

ACT374

Abstract: 54ACT534DM
Contextual Info: 54ACT534 Octal D Flip-Flop with TRI-STATE Outputs General Description The ’ACT534 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable (OE) are common to all

Contextual Info: LCD-GRAPHIC MODULE 9.2008 160x128 WITH CONTROLLER T6963 Outline dimensions: 140x102x16mm FEATURES * * * * * * * * * HIGH CONTRAST STN TECHNOLOGY, NEGATIVE BLUE, BOTTOM VIEW CONTROLLER T6963C BUILT-IN 8-BIT BUS INTERFACE ASCII CHARACTER SET BUILT-IN DISPLAY TEXT AND GRAPHIC SIMULTANEOUSLY

ECL 100315

Contextual Info: 100315 Low-Skew Quad Clock Driver General Description The 100315 contains four low skew differential drivers, designed for generation of multiple, minimum skew differential clocks from a single differential input. This device also has the capability to select a secondary single-ended clock

26LS31C

Abstract: DS26LS31CMX ds26ls31 ds26ls31m
Contextual Info: DS26LS31C/DS26LS31M Quad High Speed Differential Line Driver General Description Features The DS26LS31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26LS31 meets all the requirements of EIA Standard RS-422 and Federal Standard 1020. It is designed to provide

Contextual Info: 54F 74F378 Parallel D Register with Enable General Description Features The ’F378 is a 6-bit register with a buffered common Enable This device is similar to the ’F174 but with common Enable rather than common Master Reset Y Y Y Y Y Commercial Military

Contextual Info: 54F 74F191 Up Down Binary Counter with Preset and Ripple Clock General Description Features The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting The preset feature allows the ’F191 to be used in programmable dividers The Count Enable input the Terminal Count

IC ax 2008 USB FM PLAYER

Abstract: STi7110 IC ax 2008 used for mp3 player le88221 PI7C9X440SL PI7C9X111SL bl3458 pi3eqx6701 PI3EQX5701 PAS5201
Contextual Info: Table of Contents PAGE 2 3 About Pericom Applications 13 Products - Signal Integrity 14 17 18 19 PCI Express ReDriver SAS/SATA/XAUI ReDriver Digital Video Signal Integrity DisplayPort, HDMI, DVI USB3 ReDriver 21 Products - Connectivity 23 25 27 33 35 45

Contextual Info: DS26LS32AC/DS26LS32C/DS26LS32M/DS26LS33M Quad Differential Line Receivers General Description Features The DS26LS32 and DS26LS32A are quad differential line receivers designed to meet the RS-422, RS-423 and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission.

26C31M

Abstract: DS26C31TN
Contextual Info: DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver General Description The DS26C31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26C31T meets all the requirements of EIA standard RS-422 while retaining the low power characteristics of

90LV031A

Abstract: DS90LV031AW-QML LV031ATM
Contextual Info: DS90LV031A 3V LVDS Quad CMOS Differential Line Driver General Description Features The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data