ZL30462 Search Results

ZARLINK FPGA

Abstract: GR-1244-CORE GR-253-CORE TR62411 ZL30462 ZL30462MCF
Contextual Info: Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ZL30462

BELLCORE T1 standards

Contextual Info: 19.440 MHz 2.048 MHz 1.544 MHz 8 KHz Hitless Reference Switching TIE Correction Slope Limiter SONET Stratum 3 SDH Mode Automatic Holdover Mode Holdover Indication ZL30462 2 l l l l l l l l l ZL30461 2 l l l l l l l l l l l l l l www.ZARLINK.com l l l 4 /4E

MS2 IR

Contextual Info: ZL30462 Compact Timing Module Data Sheet Features January 2005 • Complete timing solution in a small outline package • 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz input reference frequencies • 8 kHz frame pulse , 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz and two 155.52 MHz

pcci

Abstract: zt100 mux circuit
Contextual Info: ZL30462 Timing Module Data Sheet Features • • • • • • • • • April 2003 Complete timing solution in a small outline package Selectable 8kHz, 1.544MHz, 2.048MHz or 19.44MHz input reference frequencies 8kHz frame pulses , 2.048MHz, 8.192MHz,

GR-1244-CORE

Abstract: GR-253-CORE TR62411 ZL30462 ZL30462MCF
Contextual Info: ZL30462 Compact Timing Module Data Sheet Features November 2003 • Complete timing solution in a small outline package • 8kHz, 1.544MHz, 2.048MHz or 19.44MHz input reference frequencies • 8kHz frame pulse , 2.048MHz, 8.192MHz, 16.384MHz, 19.44MHz and two 155.52MHz

GR-1244-CORE

Abstract: GR-253-CORE TR62411 ZL30462 ZL30462MCF FA-104 FA104
Contextual Info: ZL30462 Compact Timing Module Data Sheet Features November 2003 • Complete timing solution in a small outline package • 8kHz, 1.544MHz, 2.048MHz or 19.44MHz input reference frequencies • 8kHz frame pulse , 2.048MHz, 8.192MHz, 16.384MHz, 19.44MHz and two 155.52MHz

digital clock circuit diagram

Abstract: ja155
Contextual Info: ZLAN-28 Applications of the ZL30462 Timing Module Application Note Contents October 2003 provides designers with information on implementing this module in a timing solution. This document should be used in conjunction with the ZL30462 data sheet. 1.0 Summary

zarlink label

Abstract: ZL30462 Zarlink Semiconductor
Contextual Info: ZLAN-70 Applications of the ZL30462 Manufacturing Guidelines Application Note Contents November 2003 1.0 Operating Temperature 2.0 Storage Temperature 3.0 Use & Storage 4.0 Reflow parameters 5.0 Reel Characteristics 1.0 4.0 Surface mount product suitable for Convection reflow

J19D

Contextual Info: ZL30462 Compact Timing Module Data Sheet Features November 2003 • Complete timing solution in a small outline package • 8kHz, 1.544MHz, 2.048MHz or 19.44MHz input reference frequencies • 8kHz frame pulse , 2.048MHz, 8.192MHz, 16.384MHz, 19.44MHz and two 155.52MHz

Contextual Info: ZL30462 TIMING MODULE VOICE / DATA ZL30462 Simplified Block Diagram Timing Module Stratum 4/4E Digital PLL Reference Input Clocks 8kHz, 1.544MHz, 2.048MHz, 19.44MHz Primary Reference Secondary Reference Master Oscillator 20Mhz Dual Reference Frequency Selection

Contextual Info: ZL30461 COMPACT STRATUM 3 TIMING MODULE VOICE / DATA ZL30461 Simplified Block Diagram 9ecfWYjIjhWjkc J_c_d]CeZkb[ Acquisition PLLs 8 kHz, 1.5, 2 & 19 MHz Primary Reference Independant Frequency Detection & Monitoring Secondary Reference Core Digital PLL