DSAQ00183030.pdf by Cypress Semiconductor

Partial File Text 18-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C116
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3M Touch Systems