DSA0066480.pdf
by Cypress Semiconductor
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CY7C12461KV18, CY7C12571KV18
CY7C12481KV18, CY7C12501KV18
36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Functional Description
36-Mbit Density (4M x
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Original
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Unknown
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Unknown
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Unknown
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Find it at Findchips.com
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