74HC112DB,118 datasheet by NXP Semiconductors

Description dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; F<sub>max</sub>: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13"
Datasheet Type Original
RoHS Yes
Lifecycle Transferred
HTS Code 8542.39.00.01
Schedule B 8542.39.00.00
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74HC112DB,118 datasheet preview Download Datasheet