74HC112N,652 datasheet by NXP Semiconductors

Description dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; F<sub>max</sub>: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC
Datasheet Type Original
RoHS Yes
Pb Free Unknown
Lifecycle Obsolete
HTS Code 8542.39.00.01
Schedule B 8542.39.00.00
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Equivalent Parts !
Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.

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74HC112N,652 datasheet preview

The recommended operating voltage range for the 74HC112N,652 is 2.0 V to 6.0 V, with a typical voltage of 5.0 V.
Unused inputs of the 74HC112N,652 should be connected to VCC or GND to prevent them from floating and causing unintended behavior.
The maximum frequency of operation for the 74HC112N,652 is typically around 100 MHz, but this can vary depending on the specific application and operating conditions.
Yes, the 74HC112N,652 can be used in a 3.3V system, but the output voltage will be limited to around 3.0V, and the device may not meet the specified propagation delay and transition times.
To ensure the 74HC112N,652 is properly powered, a decoupling capacitor of 0.1 μF to 1.0 μF should be placed as close as possible to the VCC pin, and the power supply should be able to provide sufficient current to meet the device's operating requirements.

74HC112N,652 datasheet preview Download Datasheet