The maximum clock frequency for the 74HC165D is 25 MHz.
Yes, the 74HC165D can be used as a parallel-in, serial-out shift register. The parallel data is loaded into the shift register on the rising edge of the clock signal when the parallel load input (PL) is low.
The 74HC165D can be reset by applying a low signal to the reset input (R) and then bringing it high. This clears the shift register and sets the output (QH) to low.
The propagation delay time for the 74HC165D is typically 10 ns (Tamb = 25°C).
Yes, the 74HC165D is compatible with 5V systems. It operates from a supply voltage range of 2V to 6V.
74HC165D,653 datasheet
by NXP Semiconductors
