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    Part Img 74HC4059N,112 datasheet by NXP Semiconductors

    • programmable divide-by-n counter - Description: Programmable Divide-By-N Counter ; F<sub>max</sub>: 43 MHz; Logic switching levels: CMOS ; Number of pins: 24 ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT101-1 (DIP24); Container: Bulk Pack
    • Original
    • Yes
    • Unknown
    • Obsolete
    • 8542.39.00.01
    • 8542.39.00.00
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    74HC4059N,112 datasheet preview

    74HC4059N,112 Frequently Asked Questions (FAQs)

    • The recommended operating voltage range for the 74HC4059N,112 is 2V to 6V, with a typical voltage of 5V.
    • To ensure proper power supply, connect VCC to a stable voltage source, and GND to a solid ground. Decouple the power supply with a 0.1uF capacitor to reduce noise and ensure reliable operation.
    • The maximum clock frequency that the 74HC4059N,112 can handle is 30 MHz, but this may vary depending on the specific application and operating conditions.
    • The output enable (OE) pin is active-low, meaning that when it is low, the outputs are enabled. When OE is high, the outputs are in a high-impedance state. Ensure that OE is properly connected to a logic signal or a pull-up resistor to avoid unintended output states.
    • The propagation delay of the 74HC4059N,112 is typically around 10-15 ns, but this may vary depending on the specific application, operating conditions, and output load.
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