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3.3V CMOS 16-BIT TRANSÂ
PARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FE A T U R E S :
-
-
0.5 MICRON CMOS Technology
Typical tsK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD