DSA00435015.pdf by Xilinx

Partial File Text Application Note: Virtex Series R XAPP222 (v1.0) September 27, 2000 Summary Designing Convolutional Interleavers with Virtex Devices Author: Gianluca Gilardi and Catello Antonio De Rosa
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32-Bit Parallel-IN parallel-OUT Shift Register 32-Bit Parallel-IN Serial-OUT Shift Register 32-Bit sipo Shift Register 5 to 32 decoder using 3 to 8 decoder vhdl code Convolutional convolutional interleaver design for block interleaver deinterleaver DS003 interleaver interleaver by vhdl interleaver time parallel to serial conversion vhdl real time application of D flip-flop sipo shift register by using D flip-flop SRL16 vhdl code for asynchronous piso vhdl code for bit interleaver vhdl code for block interleaver vhdl code for interleaver vhdl code for parallel to serial converter vhdl code for parallel to serial shift register vhdl code for phase shift vhdl code for shift register using d flipflop vhdl code for sipo vhdl code for sipo piso XAPP130 XAPP222 XC4062XL XC5210 XCV200 XCV400E

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