DSA00202069.pdf by Cypress Semiconductor

Partial File Text CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description 36-Mbit density (4M x 8, 4M x
Datasheet Type Original
RoHS Unknown
Pb Free Unknown
Lifecycle Unknown
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CY7C1246V18 CY7C1248V18 CY7C1250V18 CY7C1257V18