The recommended power-on sequence is to apply VDD (analog supply) first, followed by VIO (digital supply) and then the clock signal. This ensures proper initialization of the device.
To optimize the analog input impedance, use a low-impedance source (e.g., a buffer amplifier) and keep the input traces as short as possible. Additionally, use a capacitor (e.g., 10nF) in parallel with the input resistor to filter out high-frequency noise.
The maximum clock frequency for the ADS7886 is 20 MHz. However, the device can operate at higher frequencies with reduced performance. Consult the datasheet for more information on clock frequency vs. performance trade-offs.
During power-down mode, the SDO pin is high-impedance. To prevent unwanted current consumption, connect the SDO pin to a pull-down resistor (e.g., 1kΩ) to ensure it remains low during power-down.
Separate the analog and digital grounds to minimize noise coupling. Use a single-point ground connection for the analog ground and a separate ground plane for the digital ground. Keep the analog ground traces as short as possible and away from digital signals.
ADS7886SBDCKT datasheet
by Texas Instruments
