The recommended layout and routing for the ADS7950SBRGER involves keeping the analog and digital grounds separate, using a solid ground plane, and minimizing the length of the analog input traces. It's also recommended to use a 4-layer PCB with a dedicated analog power plane and a dedicated digital power plane.
To optimize the performance of the ADS7950SBRGER in noisy environments, use a low-pass filter at the input, use a shielded cable for the analog input, and consider using a common-mode filter or a differential amplifier to reject common-mode noise. Additionally, ensure that the analog and digital grounds are properly separated and decoupled.
The maximum sampling rate of the ADS7950SBRGER is 1.5 MSPS (mega-samples per second). However, the actual sampling rate may be limited by the system clock frequency, the conversion time, and the settling time of the analog input signal.
The ADS7950SBRGER does not require calibration in the classical sense. However, it's recommended to perform a system-level calibration to ensure that the ADC is operating within the specified accuracy. This can be done by applying a known input voltage and measuring the output code to determine the gain and offset errors.
The power consumption of the ADS7950SBRGER depends on the operating mode and the clock frequency. In normal operation, the typical power consumption is around 35 mW at 1.5 MSPS. In power-down mode, the typical power consumption is around 10 μW.
ADS7950SBRGER datasheet
by Texas Instruments
