A good layout and routing practice is to keep the analog and digital grounds separate, use a solid ground plane, and keep the analog and digital signal traces separate and away from each other. Additionally, use a low-ESR capacitor for the AVDD and DVDD pins, and decouple the REFIO pin with a 10nF capacitor.
The internal reference voltage can be configured by connecting the REFIO pin to a capacitor (typically 10nF) to ground, and then connecting the REF pin to the desired reference voltage (e.g. 2.5V or 4.096V). The internal reference voltage can also be bypassed by connecting the REFIO pin to an external reference voltage.
The recommended clock frequency for the ADS8361IDBQR is between 1MHz to 20MHz. A clock source with low jitter and noise is recommended, such as a crystal oscillator or a high-quality clock generator. The clock input should be connected to the CLK pin, and the clock frequency should be set according to the desired sampling rate.
The digital output data from the ADS8361IDBQR is in two's complement format, with the most significant bit (MSB) first. The data is output on the D[15:0] pins, with the MSB on D15 and the least significant bit (LSB) on D0. The data is output in serial format, with one bit per clock cycle, and can be latched into a register or FIFO for further processing.
The POR timing for the ADS8361IDBQR is typically around 10ms, during which the device is in a reset state. After the POR, the device takes around 100us to 200us to stabilize and become operational. It is recommended to wait for at least 1ms after power-on before initiating any conversions.
ADS8361IDBQR datasheet
by Texas Instruments
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