Texas Instruments recommends a 4-layer PCB with a solid ground plane, and to keep the analog and digital signals separate. Use short, direct traces for the analog inputs and outputs, and avoid running digital signals near the analog signals. Additionally, use a common-mode filter capacitor between the analog input and the analog ground to reduce noise.
The ADS850Y/2K has an internal calibration circuit that can be enabled by setting the CAL pin high. During calibration, the device adjusts its internal offset and gain to ensure accurate conversions. It's recommended to perform calibration after power-up and whenever the device is reset. Refer to the datasheet for the specific calibration procedure.
The maximum sampling rate of the ADS850Y/2K is 200 kSPS. However, the actual sampling rate may be limited by the system's clock frequency, the analog input bandwidth, and the digital output data rate. Increasing the sampling rate will also increase the power consumption, so it's essential to balance the sampling rate with power consumption requirements.
The ADS850Y/2K outputs 16-bit or 18-bit data, depending on the mode selected. The output data format can be either binary two's complement or offset binary. The device also provides a data-ready signal (DRDY) to indicate when the conversion is complete. The output data can be accessed through the SPI or parallel interface.
The reference voltage (VREF) should be selected based on the desired input range and the required accuracy. A stable, low-noise reference voltage is essential for accurate conversions. The VREF pin can be connected to an external reference voltage source or to the internal reference voltage generator. Ensure that the VREF voltage is within the recommended range (2.5 V to 5 V) and that it's properly decoupled to minimize noise.
ADS850Y/2K datasheet
by Texas Instruments
