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    Part Img CD74AC112M96 datasheet by Texas Instruments

    • Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125
    • Original
    • Yes
    • Yes
    • Active
    • EAR99
    • 8542.39.00.01
    • 8542.39.00.00
    • Find it at Findchips.com

    CD74AC112M96 datasheet preview

    CD74AC112M96 Frequently Asked Questions (FAQs)

    • The CD74AC112M96 can handle clock frequencies up to 100 MHz.
    • The CD74AC112M96 requires a power supply voltage (VCC) of 2.0V to 6.0V, and it is recommended to use a decoupling capacitor of 0.1uF to 1uF between VCC and GND to ensure proper power supply decoupling.
    • The propagation delay of the CD74AC112M96 is typically around 10ns to 15ns, depending on the operating frequency and voltage.
    • Yes, the CD74AC112M96 is compatible with 3.3V systems, but it is recommended to use a voltage regulator to ensure a stable 3.3V supply.
    • The output enable (OE) pin is active-low, meaning that the outputs are enabled when OE is low (GND) and disabled when OE is high (VCC).
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