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    Part Img CD74HC73M datasheet by Texas Instruments

    • CD74HC73 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125
    • Original
    • No
    • Obsolete
    • EAR99
    • 8542.39.00.01
    • 8542.39.00.00
    • Find it at Findchips.com

    CD74HC73M datasheet preview

    CD74HC73M Frequently Asked Questions (FAQs)

    • The CD74HC73M can operate at frequencies up to 25 MHz.
    • The CD74HC73M requires a power supply voltage (VCC) of 2.0 V to 6.0 V, and it is recommended to decouple the power supply with a 0.1 μF capacitor.
    • The propagation delay time (tpd) for the CD74HC73M is typically around 10 ns, but it can vary depending on the operating conditions and load capacitance.
    • Yes, the CD74HC73M is compatible with 3.3 V systems, but it is recommended to check the voltage tolerance of the device and ensure that it meets the system's voltage requirements.
    • The output enable (OE) pin is active-low, meaning that the output is enabled when OE is low (0 V) and disabled when OE is high (VCC).
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