The recommended power-up sequence is to apply VCC first, followed by VDD, and then the input clock signal. This ensures proper device operation and prevents potential latch-up conditions.
To ensure the CDCE949PW is in a known state after power-up, assert the reset pin (RST) low for at least 10 ns to reset the device. Then, release the reset pin to allow the device to start operating normally.
The CDCE949PW can support input clock frequencies up to 200 MHz. However, the maximum frequency may vary depending on the specific application and output frequency requirements.
To optimize the CDCE949PW for low power consumption, ensure that the input clock signal is clean and free of noise, use the lowest possible input clock frequency, and disable any unused outputs. Additionally, consider using the device's power-down mode when not in use.
To ensure proper operation and minimize noise, follow good PCB layout and routing practices, such as keeping clock signals away from analog signals, using short traces, and avoiding vias and right-angle turns.
CDCE949PW datasheet
by Texas Instruments
