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    Part Img CDCP1803RGET datasheet by Texas Instruments

    • 1:3 LVPECL Clock Buffer with Programable Divider
    • Original
    • Yes
    • Yes
    • Active
    • EAR99
    • 8542.39.00.01
    • 8542.39.00.00
    • Find it at Findchips.com

    CDCP1803RGET datasheet preview

    CDCP1803RGET Frequently Asked Questions (FAQs)

    • A 4-layer PCB with a solid ground plane and a separate power plane is recommended. Keep the input and output traces short and away from each other to minimize noise and crosstalk.
    • Ensure that the output capacitor is properly sized and placed close to the output pin. Also, add a 10nF-100nF capacitor between the VCC and GND pins to filter out noise.
    • The maximum input voltage is 6.5V, but it's recommended to keep it below 5.5V to ensure reliable operation and prevent damage to the device.
    • The output voltage ripple can be calculated using the formula: ΔVout = (Iout * ESL) / (Cout * fsw), where ESL is the equivalent series inductance of the output capacitor, Cout is the output capacitance, and fsw is the switching frequency.
    • A 10uF-22uF ceramic or X5R/X7R capacitor is recommended for the input capacitor, placed as close to the VIN pin as possible.
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