CY7C1250V18-333BZC datasheet
by Cypress Semiconductor
- 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
- Original
- No
- Obsolete
- 3A991.B.2.A
- 8542.32.00.41
- 8542.32.00.40
- Find it at Findchips.com
