CY7C1250V18-333BZXC datasheet by Cypress Semiconductor

Description 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II+ CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
Datasheet Type Original
RoHS Yes
Lifecycle Obsolete
ECCN 3A991.B.2.A
HTS Code 8542.32.00.41
Schedule B 8542.32.00.40
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CY7C1250V18-333BZXI

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