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    Part Img CY7C1460AV25-200BZXI datasheet by Cypress Semiconductor

    • 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
    • Original
    • Yes
    • Yes
    • Obsolete
    • 3A991.B.2.A
    • 8542.32.00.41
    • 8542.32.00.40
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    CY7C1460AV25-200BZXI datasheet preview

    CY7C1460AV25-200BZXI Frequently Asked Questions (FAQs)

    • The CY7C1460AV25-200BZXI has an operating temperature range of 0°C to 70°C (commercial grade) and -40°C to 85°C (industrial grade).
    • To implement self-refresh mode, assert the SREF input low and ensure that the clock is stopped. This will reduce power consumption to a minimum.
    • The CY7C1460AV25-200BZXI supports a maximum clock frequency of 200 MHz.
    • To handle data retention during power-down, use the SLEEP mode. In this mode, the device will retain data and can be quickly restored to active mode when power is reapplied.
    • The latency for a read or write operation is 2 clock cycles for the CY7C1460AV25-200BZXI.
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