The recommended power-on sequence is to apply VDD first, followed by VIO. This ensures that the internal voltage regulators are powered up correctly.
To configure the MMA8653FCR1 for low-power mode, set the LPEN bit in the CTRL_REG1 register to 1. This reduces the current consumption to approximately 10 μA.
The INTSU and INTSD pins are interrupt pins that can be configured to generate interrupts based on specific events, such as data ready, motion detection, or free-fall detection.
Calibration involves applying a known acceleration to the device and adjusting the offset registers (OFF_X, OFF_Y, OFF_Z) to achieve a zero-g output. The datasheet provides a detailed calibration procedure.
The MMA8653FCR1 can measure accelerations up to ±8g, but the maximum range can be adjusted by setting the FS bit in the CTRL_REG1 register to 0 (±2g), 1 (±4g), or 2 (±8g).