PCK953BD,128 datasheet
by NXP Semiconductors
- 20-125 MHz PECL input/ 9 CMOS output 3.3 V PLL clock driver - Application: High-performance clock tree design, NG-DIMMs ; Inputs: 1 x Differential PECL ; Jitter (pk-pk): 55 ps; Operating temperature: 0~+70 Cel; Other features: output disable, bypass, 1:18 effective fan-out ; Output frequency range: 50~125 MHz; Output skew: 100 ps; Outputs: 9 x LVCMOS ; Phase offset: 60 ps; Programmability: Pin select ; Supply voltage: 3.3 V; Package: SOT358-1 (LQFP32); Container: Reel Pack, SMD, 13", Turned
- Original
- No
- Obsolete
- 8542.39.00.01
- 8542.39.00.00
- Find it at Findchips.com
