PCM1760U datasheet by Texas Instruments

PCM1760U Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the PCM1760U?
  The recommended power-up sequence is to apply VCC first, followed by VDD, and then the clock signal. This ensures that the internal voltage regulators are powered up correctly and the device is properly initialized.
• How do I configure the PCM1760U for master clock mode?
  To configure the PCM1760U for master clock mode, set the MCLK pin as an output by setting the MCLKOE bit in the Control Register (CR) to 1. Then, set the desired clock frequency using the MCLKDIV bits in the CR. The PCM1760U will then generate the master clock signal on the MCLK pin.
• What is the maximum allowed jitter on the clock input?
  The maximum allowed jitter on the clock input is 500 ps peak-to-peak. Exceeding this limit may cause errors in the audio data conversion.
• How do I handle the PCM1760U's digital output data format?
  The PCM1760U's digital output data format is 24-bit, MSB-first, and left-justified. The data is output on the DOUT pins in a serial format, with the most significant bit (MSB) first. The user must ensure that the receiving device is configured to accept this data format.
• What is the recommended layout and routing for the PCM1760U's analog and digital signals?
  To minimize noise and interference, it is recommended to separate the analog and digital signal traces on the PCB, and to use a ground plane to shield the analog signals. Additionally, the analog input signals should be routed close to the device's analog input pins, and the digital output signals should be routed away from the analog input signals.