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    Part Img PCM1792ADBR datasheet by Texas Instruments

    • 132dB SNR Highest Performance Stereo DAC (S/W Control) 28-SSOP -25 to 85
    • Original
    • Yes
    • Yes
    • Active
    • EAR99
    • 8542.39.00.01
    • 8542.39.00.00
    • Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.

    PCM1792ADBR datasheet preview

    PCM1792ADBR Price & Stock

    Distributor Stock Lead Time Min Order Qty Price Buy
    DigiKey () 1,327 1
    • 1 $16.82
    • 10 $13.35
    • 100 $11.53
    • 1000 $10.80
    • 10000 $10.80
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    1,327 1
    • 1 $16.82
    • 10 $13.35
    • 100 $11.53
    • 1000 $10.80
    • 10000 $10.80
    Buy Now
    2,000
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $9.88
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    Mouser Electronics () 329
    • 1 $15.82
    • 10 $12.84
    • 100 $11.24
    • 1000 $10.22
    • 10000 $9.81
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    32
    • 1 $24.06
    • 10 $18.82
    • 100 $15.89
    • 1000 $15.17
    • 10000 $15.17
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    23
    • 1 $24.05
    • 10 $18.81
    • 100 $16.07
    • 1000 $14.59
    • 10000 $14.59
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    Verical 1,866 1
    • 1 $10.34
    • 10 $9.68
    • 100 $9.60
    • 1000 $9.47
    • 10000 $9.47
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    Arrow Electronics 1,866 18 Weeks 1
    • 1 $10.34
    • 10 $9.68
    • 100 $9.60
    • 1000 $9.47
    • 10000 $9.47
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    Vyrian () 7,331
    • 1 -
    • 10 -
    • 100 -
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    1,097
    • 1 -
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    PCM1792ADBR Frequently Asked Questions (FAQs)

    • The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures that the analog and digital circuits are powered up in the correct order.
    • To optimize the PCB layout, keep analog and digital signals separate, use a solid ground plane, and place decoupling capacitors close to the device. Also, ensure that the clock signal traces are short and direct to minimize jitter.
    • The maximum clock frequency supported by the PCM1792ADBR is 256 fs (where fs is the sampling frequency). For example, at a sampling frequency of 44.1 kHz, the maximum clock frequency is 11.2896 MHz.
    • To configure the PCM1792ADBR for master clock mode, set the MCLK pin to the desired clock frequency, and set the M/S pin to logic high. Also, ensure that the BCK pin is connected to the clock signal and the LRCK pin is connected to the frame clock signal.
    • The recommended termination for the PCM1792ADBR's digital outputs is a 50-ohm resistor in series with a 10-pF capacitor to ground. This helps to reduce electromagnetic interference (EMI) and improve signal integrity.
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