PCM1794DB datasheet by Texas Instruments

PCM1794DB Frequently Asked Questions (FAQs)

• What is the recommended power-up sequence for the PCM1794DB?
  The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures that the internal voltage regulators are powered up correctly.
• How do I optimize the PCB layout for the PCM1794DB?
  To optimize the PCB layout, keep the analog and digital grounds separate, use a solid ground plane, and keep the analog signals away from the digital signals. Also, use a low-ESR capacitor for the AVCC and DVCC pins.
• What is the maximum clock frequency that the PCM1794DB can support?
  The maximum clock frequency that the PCM1794DB can support is 256 fs (where fs is the sampling frequency). For example, for a sampling frequency of 192 kHz, the maximum clock frequency is 49.152 MHz.
• How do I configure the PCM1794DB for Master Clock mode?
  To configure the PCM1794DB for Master Clock mode, set the MCLK pin to the desired clock frequency, and set the BCK pin to the desired bit clock frequency. Also, set the LRCK pin to the desired left-right clock frequency.
• What is the recommended value for the external clock capacitor (CCLK) in the PCM1794DB?
  The recommended value for the external clock capacitor (CCLK) is 10 nF to 100 nF. This capacitor helps to filter the clock signal and reduce jitter.