The recommended power-up sequence is to apply VCC first, followed by AVDD, and then DVDD. This ensures that the internal voltage regulators are powered up correctly.
To optimize the analog input impedance, use a series resistor (Rs) and a capacitor (Cs) in parallel with the input signal. The values of Rs and Cs depend on the specific application and signal frequency.
The maximum clock frequency for the PCM3002EG is 256 fs (fs = sample frequency). However, it's recommended to use a clock frequency that is 4-6 times the sample frequency to ensure proper operation.
To minimize clock jitter, use a high-quality clock source, such as a crystal oscillator, and ensure that the clock signal is properly terminated and filtered. Additionally, use a clock jitter attenuator or a phase-locked loop (PLL) to further reduce jitter.
To minimize noise and ensure proper operation, follow a star-grounding layout, keep analog and digital signals separate, and use a solid ground plane. Also, route the clock signal as a differential pair and use a shielded cable for the analog input signals.
PCM3002EG datasheet
by Texas Instruments
